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authorMax Krummenacher <max.krummenacher@toradex.com>2018-06-28 18:43:27 +0200
committerPhilippe Schenker <philippe.schenker@toradex.com>2019-05-09 11:13:54 +0200
commit8723afa1bd8a466d659b9e35957e54fa0f922ca9 (patch)
treeaae4914b81629edb0472dcffabe7d2448e23c516
parentf2a761b301aa0d198128cda03f3670efc1cc87f2 (diff)
ARM: dts: Coibri iMX6ULL: use wdog HW signal for reset
The i.MX6 ULL's watchdog is used to reset the SoC on reboot. The watchdog is configured to use the SoC's internal reset signal which does not generate a reset pulse on nRESET_OUT. Change the watchdog configuration to use a SoC external HW signal. This will additionally change the 'Reset cause' message from U-Boot from WDOG to POR. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
-rw-r--r--arch/arm/boot/dts/imx6ull-colibri.dtsi12
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi
index 25aad2654424..75d959c64284 100644
--- a/arch/arm/boot/dts/imx6ull-colibri.dtsi
+++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi
@@ -514,6 +514,12 @@
MX6UL_PAD_GPIO1_IO03__REF_CLK_32K 0x14
>;
};
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
+ >;
+ };
};
};
@@ -628,3 +634,9 @@
assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
assigned-clock-rates = <0>, <198000000>;
};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+};