diff options
| author | Stefan Agner <stefan.agner@toradex.com> | 2018-03-19 10:52:08 +0100 |
|---|---|---|
| committer | Philippe Schenker <philippe.schenker@toradex.com> | 2019-05-09 11:13:53 +0200 |
| commit | f33f592f77af45f594804958777b068486e21683 (patch) | |
| tree | bf384aa4e5221d119200f886c50396b0a9b8f8de | |
| parent | 1badaab8bd0aa57e9adc335ee60b852e9bf74811 (diff) | |
Revert "MLK-15120 ARM: imx7d: clk: select uart3 clock parent and set rate"
This seems to limit possible baud rates due to lower input clock.
Since Toradex modules do not use UART3 as console, do not set
clock explicitly.
This reverts commit 89869792e2f59c81354f9a53280c4eb6e95f4a9a.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
| -rw-r--r-- | drivers/clk/imx/clk-imx7d.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c index 363060a851f2..041d7b54f0e2 100644 --- a/drivers/clk/imx/clk-imx7d.c +++ b/drivers/clk/imx/clk-imx7d.c @@ -921,8 +921,6 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) /* set parent of SIM1 root clock */ imx_clk_set_parent(clks[IMX7D_SIM1_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_120M_CLK]); - imx_clk_set_parent(clks[IMX7D_UART3_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]); - imx_clk_set_rate(clks[IMX7D_UART3_ROOT_DIV], 80000000); imx_clk_set_parent(clks[IMX7D_UART5_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]); imx_clk_set_rate(clks[IMX7D_UART5_ROOT_DIV], 80000000); imx_clk_set_parent(clks[IMX7D_UART6_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]); |