diff options
| author | Fugang Duan <fugang.duan@nxp.com> | 2019-06-05 18:36:02 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:04:31 +0800 |
| commit | 6fac62a282c7d221be17c16f2abe7a93517477cb (patch) | |
| tree | e7d2fabfb448b8a944337ee912970afb6d77ca58 | |
| parent | 09c09cbf91d7edd47417e2d8c936b0505ad13d69 (diff) | |
arm64: dts: imx8qxp: enable enet1 port
Currently enet cannot work due to the wrong clock tree and
incorrect IO voltage, correct them.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi | 14 | ||||
| -rwxr-xr-x | arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 6 | ||||
| -rw-r--r-- | include/dt-bindings/pinctrl/pads-imx8qxp.h | 24 |
3 files changed, 40 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi index 80dc000889bc..163eefa9a9c9 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi @@ -107,9 +107,12 @@ conn_subsys: bus@5b000000 { <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>, <&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>; + <&conn_lpcg IMX_CONN_LPCG_ENET0_RGMII_TXC_CLK>, + <&conn_lpcg IMX_CONN_LPCG_ENET0_TIMER_CLK>; clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; + assigned-clocks = <&clk IMX_CONN_ENET0_ROOT_CLK>, + <&clk IMX_CONN_ENET0_REF_DIV>; + assigned-clock-rates = <250000000>, <125000000>; fsl,num-tx-queues=<3>; fsl,num-rx-queues=<3>; power-domains = <&pd IMX_SC_R_ENET_0>; @@ -125,9 +128,12 @@ conn_subsys: bus@5b000000 { <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>, <&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>, - <&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>; + <&conn_lpcg IMX_CONN_LPCG_ENET1_RGMII_TXC_CLK>, + <&conn_lpcg IMX_CONN_LPCG_ENET1_TIMER_CLK>; clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; + assigned-clocks = <&clk IMX_CONN_ENET1_ROOT_CLK>, + <&clk IMX_CONN_ENET1_REF_DIV>; + assigned-clock-rates = <250000000>, <125000000>; fsl,num-tx-queues=<3>; fsl,num-rx-queues=<3>; power-domains = <&pd IMX_SC_R_ENET_1>; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index bbff2fae2cef..8a8169325564 100755 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -447,11 +447,15 @@ ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; + at803x,eee-disabled; + at803x,vddio-1p8v; }; ethphy1: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; + at803x,eee-disabled; + at803x,vddio-1p8v; }; }; }; @@ -765,6 +769,8 @@ pinctrl_fec1: fec1grp { fsl,pins = < + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 diff --git a/include/dt-bindings/pinctrl/pads-imx8qxp.h b/include/dt-bindings/pinctrl/pads-imx8qxp.h index fbfee7ecf844..bfe9ab7c684c 100644 --- a/include/dt-bindings/pinctrl/pads-imx8qxp.h +++ b/include/dt-bindings/pinctrl/pads-imx8qxp.h @@ -748,4 +748,28 @@ #define IMX8QXP_QSPI0B_SS1_B_LSIO_KPP0_ROW3 IMX8QXP_QSPI0B_SS1_B 2 #define IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24 IMX8QXP_QSPI0B_SS1_B 4 +/*! + * @name Fake Pad Mux Definitions + * format: name padid 0 + */ +/*@{*/ +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_PCIESEP_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_PCIESEP 0 +#define IMX8QXP_COMP_CTL_GPIO_3V3_USB3IO_PAD IMX8QXP_COMP_CTL_GPIO_3V3_USB3IO 0 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 0 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 0 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_VSELSEP_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_VSELSEP 0 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_VSEL3_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_VSEL3 0 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 0 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 0 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIOCT_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIOCT 0 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB 0 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHK 0 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHT_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHT 0 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIOLH_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIOLH 0 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 0 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHD_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHD 0 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0A_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0A 0 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0B_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0B 0 +/*@}*/ + #endif /* _IMX8QXP_PADS_H */ |