diff options
author | Liu Ying <victor.liu@nxp.com> | 2019-08-07 11:50:59 +0800 |
---|---|---|
committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:05:33 +0800 |
commit | 79d1b7a317d3c076707d886f76ab1947bbf68cb0 (patch) | |
tree | 336c6a3078fdc6306b78e028802f904cc1df963d | |
parent | a6d72d406b14185e5e71896913e25271de77a6aa (diff) |
arm64: imx8qxp-ss-lvds.dtsi: Rename imx8-ss-lvds.dtsi to imx8qxp-ss-lvds.dtsi
i.MX8qxp LVDS display feature is supported by MIPI DSI/LVDS combo subsystem.
i.MX8qm LVDS display feature is supported by standalone LVDS subsystem.
There is not a lot of common hardwares for the two kinds of subsytems,
so rename imx8-ss-lvds.dtsi to imx8qxp-ss-lvds.dtsi.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8-ss-lvds.dtsi | 238 | ||||
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi | 241 | ||||
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 2 |
3 files changed, 242 insertions, 239 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lvds.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lvds.dtsi deleted file mode 100644 index a4a1276d136a..000000000000 --- a/arch/arm64/boot/dts/freescale/imx8-ss-lvds.dtsi +++ /dev/null @@ -1,238 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2019 NXP - */ - -lvds_subsys: bus@56220000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x56220000 0x0 0x56220000 0x30000>; - - mipi_ipg_clk: clock-mipi-ipg { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <120000000>; - clock-output-names = "mipi_ipg_clk"; - }; - - mipi0_lis_lpcg: clock-controller@56223000 { - compatible = "fsl,imx8qxp-lpcg"; - reg = <0x56223000 0x4>; - #clock-cells = <1>; - clocks = <&mipi_ipg_clk>; - bit-offset = <16>; - clock-output-names = "mipi0_lis_lpcg_ipg_clk"; - power-domains = <&pd IMX_SC_R_MIPI_0>; - }; - - mipi0_i2c0_lpcg: clock-controller@56223010 { - compatible = "fsl,imx8qxp-lpcg"; - reg = <0x56223010 0x4>; - #clock-cells = <1>; - clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_PER>, - <&mipi_ipg_clk>; - bit-offset = <0 16>; - clock-output-names = "mipi0_i2c0_lpcg_clk", - "mipi0_i2c0_lpcg_ipg_clk"; - power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>; - }; - - mipi1_lis_lpcg: clock-controller@56243000 { - compatible = "fsl,imx8qxp-lpcg"; - reg = <0x56243000 0x4>; - #clock-cells = <1>; - clocks = <&mipi_ipg_clk>; - bit-offset = <16>; - clock-output-names = "mipi1_lis_lpcg_ipg_clk"; - power-domains = <&pd IMX_SC_R_MIPI_1>; - }; - - mipi1_i2c0_lpcg: clock-controller@56243010 { - compatible = "fsl,imx8qxp-lpcg"; - reg = <0x56243010 0x4>; - #clock-cells = <1>; - clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>, - <&mipi_ipg_clk>; - bit-offset = <0 16>; - clock-output-names = "mipi1_i2c0_lpcg_clk", - "mipi1_i2c0_lpcg_ipg_clk"; - power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>; - }; - - irqsteer_mipi_lvds0: irqsteer@56220000 { - compatible = "fsl,imx-irqsteer"; - reg = <0x56220000 0x1000>; - interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - interrupt-parent = <&gic>; - #interrupt-cells = <1>; - fsl,channel = <0>; - fsl,num-irqs = <32>; - clocks = <&mipi0_lis_lpcg 0>; - clock-names = "ipg"; - power-domains = <&pd IMX_SC_R_MIPI_0>; - }; - - lvds_region1: lvds_region@56220000 { - compatible = "syscon"; - reg = <0x56220000 0x10000>; - }; - - ldb1_phy: ldb_phy@56221000 { - compatible = "mixel,lvds-combo-phy"; - reg = <0x56221000 0x100>, <0x56228000 0x1000>; - #phy-cells = <0>; - clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC3>; - clock-names = "phy"; - power-domains = <&pd IMX_SC_R_LVDS_0>; - status = "disabled"; - }; - - ldb1: ldb@562210e0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx8qxp-ldb"; - clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>, - <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>; - clock-names = "pixel", "bypass"; - power-domains = <&pd IMX_SC_R_LVDS_0>; - gpr = <&lvds_region1>; - status = "disabled"; - - lvds-channel@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - phys = <&ldb1_phy>; - phy-names = "ldb_phy"; - status = "disabled"; - - port@0 { - reg = <0>; - - ldb1_ch0: endpoint { - remote-endpoint = <&dpu_disp0_ldb1_ch0>; - }; - }; - }; - - lvds-channel@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - phys = <&ldb1_phy>; - phy-names = "ldb_phy"; - status = "disabled"; - - port@0 { - reg = <0>; - - ldb1_ch1: endpoint { - remote-endpoint = <&dpu_disp0_ldb1_ch1>; - }; - }; - }; - }; - - i2c0_mipi_lvds0: i2c@56226000 { - compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x56226000 0x4000>; - interrupts = <8>; - interrupt-parent = <&irqsteer_mipi_lvds0>; - clocks = <&mipi0_i2c0_lpcg 0>; - clock-names = "per"; - assigned-clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_PER>; - assigned-clock-rates = <24000000>; - power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>; - status = "disabled"; - }; - - irqsteer_mipi_lvds1: irqsteer@56240000 { - compatible = "fsl,imx-irqsteer"; - reg = <0x56240000 0x1000>; - interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - interrupt-parent = <&gic>; - #interrupt-cells = <1>; - fsl,channel = <0>; - fsl,num-irqs = <32>; - clocks = <&mipi1_lis_lpcg 0>; - clock-names = "ipg"; - power-domains = <&pd IMX_SC_R_MIPI_1>; - }; - - lvds_region2: lvds_region@56240000 { - compatible = "syscon"; - reg = <0x56240000 0x10000>; - }; - - ldb2_phy: ldb_phy@56241000 { - compatible = "mixel,lvds-combo-phy"; - reg = <0x56241000 0x100>, <0x56248000 0x1000>; - #phy-cells = <0>; - clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_MISC3>; - clock-names = "phy"; - power-domains = <&pd IMX_SC_R_LVDS_1>; - status = "disabled"; - }; - - ldb2: ldb@562410e0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx8qxp-ldb"; - clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_MISC2>, - <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_BYPASS>; - clock-names = "pixel", "bypass"; - power-domains = <&pd IMX_SC_R_LVDS_1>; - gpr = <&lvds_region2>; - status = "disabled"; - - lvds-channel@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - phys = <&ldb2_phy>; - phy-names = "ldb_phy"; - status = "disabled"; - - port@0 { - reg = <0>; - - ldb2_ch0: endpoint { - remote-endpoint = <&dpu_disp1_ldb2_ch0>; - }; - }; - }; - - lvds-channel@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - phys = <&ldb2_phy>; - phy-names = "ldb_phy"; - status = "disabled"; - - port@0 { - reg = <0>; - - ldb2_ch1: endpoint { - remote-endpoint = <&dpu_disp1_ldb2_ch1>; - }; - }; - }; - }; - - i2c0_mipi_lvds1: i2c@56246000 { - compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x56246000 0x4000>; - interrupts = <8>; - interrupt-parent = <&irqsteer_mipi_lvds1>; - clocks = <&mipi1_i2c0_lpcg 0>; - clock-names = "per"; - assigned-clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>; - assigned-clock-rates = <24000000>; - power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>; - status = "disabled"; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi new file mode 100644 index 000000000000..572b10592794 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lvds.dtsi @@ -0,0 +1,241 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * Copyright 2019 NXP + */ + +/ { + lvds_subsys: bus@56220000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x56220000 0x0 0x56220000 0x30000>; + + mipi_ipg_clk: clock-mipi-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <120000000>; + clock-output-names = "mipi_ipg_clk"; + }; + + mipi0_lis_lpcg: clock-controller@56223000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56223000 0x4>; + #clock-cells = <1>; + clocks = <&mipi_ipg_clk>; + bit-offset = <16>; + clock-output-names = "mipi0_lis_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0>; + }; + + mipi0_i2c0_lpcg: clock-controller@56223010 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56223010 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_PER>, + <&mipi_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "mipi0_i2c0_lpcg_clk", + "mipi0_i2c0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>; + }; + + mipi1_lis_lpcg: clock-controller@56243000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56243000 0x4>; + #clock-cells = <1>; + clocks = <&mipi_ipg_clk>; + bit-offset = <16>; + clock-output-names = "mipi1_lis_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1>; + }; + + mipi1_i2c0_lpcg: clock-controller@56243010 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x56243010 0x4>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>, + <&mipi_ipg_clk>; + bit-offset = <0 16>; + clock-output-names = "mipi1_i2c0_lpcg_clk", + "mipi1_i2c0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>; + }; + + irqsteer_mipi_lvds0: irqsteer@56220000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x56220000 0x1000>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + fsl,channel = <0>; + fsl,num-irqs = <32>; + clocks = <&mipi0_lis_lpcg 0>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_MIPI_0>; + }; + + lvds_region1: lvds_region@56220000 { + compatible = "syscon"; + reg = <0x56220000 0x10000>; + }; + + ldb1_phy: ldb_phy@56221000 { + compatible = "mixel,lvds-combo-phy"; + reg = <0x56221000 0x100>, <0x56228000 0x1000>; + #phy-cells = <0>; + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC3>; + clock-names = "phy"; + power-domains = <&pd IMX_SC_R_LVDS_0>; + status = "disabled"; + }; + + ldb1: ldb@562210e0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qxp-ldb"; + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>, + <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>; + clock-names = "pixel", "bypass"; + power-domains = <&pd IMX_SC_R_LVDS_0>; + gpr = <&lvds_region1>; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&ldb1_phy>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb1_ch0: endpoint { + remote-endpoint = <&dpu_disp0_ldb1_ch0>; + }; + }; + }; + + lvds-channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&ldb1_phy>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb1_ch1: endpoint { + remote-endpoint = <&dpu_disp0_ldb1_ch1>; + }; + }; + }; + }; + + i2c0_mipi_lvds0: i2c@56226000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x56226000 0x4000>; + interrupts = <8>; + interrupt-parent = <&irqsteer_mipi_lvds0>; + clocks = <&mipi0_i2c0_lpcg 0>; + clock-names = "per"; + assigned-clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>; + status = "disabled"; + }; + + irqsteer_mipi_lvds1: irqsteer@56240000 { + compatible = "fsl,imx-irqsteer"; + reg = <0x56240000 0x1000>; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + fsl,channel = <0>; + fsl,num-irqs = <32>; + clocks = <&mipi1_lis_lpcg 0>; + clock-names = "ipg"; + power-domains = <&pd IMX_SC_R_MIPI_1>; + }; + + lvds_region2: lvds_region@56240000 { + compatible = "syscon"; + reg = <0x56240000 0x10000>; + }; + + ldb2_phy: ldb_phy@56241000 { + compatible = "mixel,lvds-combo-phy"; + reg = <0x56241000 0x100>, <0x56248000 0x1000>; + #phy-cells = <0>; + clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_MISC3>; + clock-names = "phy"; + power-domains = <&pd IMX_SC_R_LVDS_1>; + status = "disabled"; + }; + + ldb2: ldb@562410e0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qxp-ldb"; + clocks = <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_MISC2>, + <&clk IMX_SC_R_LVDS_1 IMX_SC_PM_CLK_BYPASS>; + clock-names = "pixel", "bypass"; + power-domains = <&pd IMX_SC_R_LVDS_1>; + gpr = <&lvds_region2>; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&ldb2_phy>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb2_ch0: endpoint { + remote-endpoint = <&dpu_disp1_ldb2_ch0>; + }; + }; + }; + + lvds-channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&ldb2_phy>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb2_ch1: endpoint { + remote-endpoint = <&dpu_disp1_ldb2_ch1>; + }; + }; + }; + }; + + i2c0_mipi_lvds1: i2c@56246000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x56246000 0x4000>; + interrupts = <8>; + interrupt-parent = <&irqsteer_mipi_lvds1>; + clocks = <&mipi1_i2c0_lpcg 0>; + clock-names = "per"; + assigned-clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index 75e43ab3c18b..9d63383c6752 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -292,7 +292,6 @@ #include "imx8-ss-cm40.dtsi" #include "imx8-ss-vpu.dtsi" #include "imx8-ss-dc0.dtsi" - #include "imx8-ss-lvds.dtsi" #include "imx8-ss-adma.dtsi" #include "imx8-ss-conn.dtsi" #include "imx8-ss-ddr.dtsi" @@ -307,6 +306,7 @@ #include "imx8qxp-ss-lsio.dtsi" #include "imx8qxp-ss-img.dtsi" #include "imx8qxp-ss-dc.dtsi" +#include "imx8qxp-ss-lvds.dtsi" &edma2 { status = "okay"; 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