diff options
author | Sandor Yu <Sandor.yu@nxp.com> | 2019-12-13 14:55:32 +0800 |
---|---|---|
committer | Sandor Yu <Sandor.yu@nxp.com> | 2019-12-16 16:14:15 +0800 |
commit | 836297fc178a8574700ef2c001b9aa032b158cac (patch) | |
tree | cef7b73eb37b634bc27f16f4d2a4a4d86f80509e | |
parent | 622141309f6e4288a4cb2f6e697c2bcbf4963fed (diff) |
LF-463-1: arm64/dts/imx8qm: Enable DPU in lpddr4 validation board
Enable DPU in lpddr4 validation board.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
-rwxr-xr-x | arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val.dts | 138 |
1 files changed, 138 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val.dts b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val.dts index 89bd8c090103..fb366f5276c4 100755 --- a/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val.dts @@ -147,6 +147,144 @@ status = "okay"; }; +&dc0_pc { + status = "okay"; +}; + +&dc0_prg1 { + status = "okay"; +}; + +&dc0_prg2 { + status = "okay"; + +}; + +&dc0_prg3 { + status = "okay"; +}; + +&dc0_prg4 { + status = "okay"; +}; + +&dc0_prg5 { + status = "okay"; +}; + +&dc0_prg6 { + status = "okay"; +}; + +&dc0_prg7 { + status = "okay"; +}; + +&dc0_prg8 { + status = "okay"; +}; + +&dc0_prg9 { + status = "okay"; +}; + +&dc0_dpr1_channel1 { + status = "okay"; +}; + +&dc0_dpr1_channel2 { + status = "okay"; +}; + +&dc0_dpr1_channel3 { + status = "okay"; +}; + +&dc0_dpr2_channel1 { + status = "okay"; +}; + +&dc0_dpr2_channel2 { + status = "okay"; +}; + +&dc0_dpr2_channel3 { + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +&dc1_pc { + status = "okay"; +}; + +&dc1_prg1 { + status = "okay"; +}; + +&dc1_prg2 { + status = "okay"; + +}; + +&dc1_prg3 { + status = "okay"; +}; + +&dc1_prg4 { + status = "okay"; +}; + +&dc1_prg5 { + status = "okay"; +}; + +&dc1_prg6 { + status = "okay"; +}; + +&dc1_prg7 { + status = "okay"; +}; + +&dc1_prg8 { + status = "okay"; +}; + +&dc1_prg9 { + status = "okay"; +}; + +&dc1_dpr1_channel1 { + status = "okay"; +}; + +&dc1_dpr1_channel2 { + status = "okay"; +}; + +&dc1_dpr1_channel3 { + status = "okay"; +}; + +&dc1_dpr2_channel1 { + status = "okay"; +}; + +&dc1_dpr2_channel2 { + status = "okay"; +}; + +&dc1_dpr2_channel3 { + status = "okay"; +}; + +&dpu2 { + status = "okay"; +}; + &sai6 { assigned-clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>, <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, |