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authorMarc Zyngier <maz@kernel.org>2019-07-16 15:18:40 +0100
committerMarc Zyngier <maz@kernel.org>2019-08-20 10:04:09 +0100
commit866246534836c60f706076cdefcd45072ad9eab2 (patch)
treed3405fd1465d4464a7319a2dc475a438cc7f9d93
parente91b036e1c20d80419164ddfc32125052df3fb39 (diff)
dt-bindings: interrupt-controller: arm,gic-v3: Describe ESPI range support
GICv3.1 introduces support for new interrupt ranges, one of them being the Extended SPI range (ESPI). The DT binding is extended to deal with it as a new interrupt class. Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Marc Zyngier <maz@kernel.org>
-rw-r--r--Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml5
1 files changed, 3 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
index c34df35a25fc..98a3ecda8e07 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
@@ -44,11 +44,12 @@ properties:
be at least 4.
The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
- interrupts. Other values are reserved for future use.
+ interrupts, 2 for interrupts in the Extended SPI range. Other values
+ are reserved for future use.
The 2nd cell contains the interrupt number for the interrupt type.
SPI interrupts are in the range [0-987]. PPI interrupts are in the
- range [0-15].
+ range [0-15]. Extented SPI interrupts are in the range [0-1023].
The 3rd cell is the flags, encoded as follows:
bits[3:0] trigger type and level flags.