diff options
| author | Harald Geyer <harald@ccbib.org> | 2018-03-15 16:25:07 +0000 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@bootlin.com> | 2018-03-19 22:12:26 +0100 |
| commit | d41850437c364ef7aba9bc25c1c701699d0240e0 (patch) | |
| tree | a6b1ec49666d404a81ce353a759fd7e077d13fb4 | |
| parent | 11239fe6a06e38a58de61d6d798afd014e770a01 (diff) | |
arm64: dts: allwinner: a64: Add watchdog
Add a watchdog node for the A64, automatically enabled on all boards.
Since the device is compatible with an existing driver, we only reserve
a new compatible string to be used together with the fall back.
Tested on Olimex Teres-I.
Signed-off-by: Harald Geyer <harald@ccbib.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
| -rw-r--r-- | Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt | 6 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 7 |
2 files changed, 11 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt b/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt index 62dd5baad70e..04fc368d828f 100644 --- a/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt @@ -2,8 +2,10 @@ Allwinner SoCs Watchdog timer Required properties: -- compatible : should be either "allwinner,sun4i-a10-wdt" or - "allwinner,sun6i-a31-wdt" +- compatible : should be one of + "allwinner,sun4i-a10-wdt" + "allwinner,sun6i-a31-wdt" + "allwinner,sun50i-a64-wdt","allwinner,sun6i-a31-wdt" - reg : Specifies base physical address and size of the registers. Example: diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 64e452a758fa..8401e7f887ff 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -665,5 +665,12 @@ #address-cells = <1>; #size-cells = <0>; }; + + wdt0: watchdog@1c20ca0 { + compatible = "allwinner,sun50i-a64-wdt", + "allwinner,sun6i-a31-wdt"; + reg = <0x01c20ca0 0x20>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + }; }; }; |