diff options
| author | Alex Frid <afrid@nvidia.com> | 2011-01-22 23:16:44 -0800 |
|---|---|---|
| committer | Niket Sirsi <nsirsi@nvidia.com> | 2011-01-25 15:27:08 -0800 |
| commit | 92bf9f72fdf696de72de6186a1e1cd8818f3bb15 (patch) | |
| tree | 95fa26bd0ace43c4fdcac5f2f1185c2cd6058b4f | |
| parent | 4c583e3e70d08f78c7b0c0bb56d6b7115e7339fe (diff) | |
ARM: tegra: dvfs: Update MPE dvfs table
Updated MPE clock dvfs table with recent characterization data.
As a result MPE clock limit is increased to 300MHz across all
tegra 2 SKUs.
Change-Id: Ibe700770c7d109a397cb140b6f217a8d48509ff1
Reviewed-on: http://git-master/r/16662
Reviewed-by: Amit Kamath <akamath@nvidia.com>
Tested-by: Amit Kamath <akamath@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/tegra2_clocks.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/tegra2_dvfs.c | 6 |
2 files changed, 6 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c index a6e732ea262a..5d566444b77a 100644 --- a/arch/arm/mach-tegra/tegra2_clocks.c +++ b/arch/arm/mach-tegra/tegra2_clocks.c @@ -2003,7 +2003,7 @@ struct clk tegra_list_clks[] = { PERIPH_CLK("vi", "tegra_camera", "vi", 20, 0x148, 0x31E, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */ PERIPH_CLK("vi_sensor", "tegra_camera", "vi_sensor", 20, 0x1a8, 0x31E, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET), /* scales with voltage and process_id */ PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 0x31E, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */ - PERIPH_CLK("mpe", "mpe", NULL, 60, 0x170, 0x31E, 250000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */ + PERIPH_CLK("mpe", "mpe", NULL, 60, 0x170, 0x31E, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */ PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 0x31E, 166000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */ PERIPH_CLK("cve", "cve", NULL, 49, 0x140, 0x31E, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */ PERIPH_CLK("tvo", "tvo", NULL, 49, 0x188, 0x31E, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */ diff --git a/arch/arm/mach-tegra/tegra2_dvfs.c b/arch/arm/mach-tegra/tegra2_dvfs.c index 74318639049c..61218af5b97f 100644 --- a/arch/arm/mach-tegra/tegra2_dvfs.c +++ b/arch/arm/mach-tegra/tegra2_dvfs.c @@ -221,7 +221,11 @@ static struct dvfs dvfs_init[] = { CORE_DVFS("3d", 2, 1, KHZ, 218500, 256500, 323000, 380000, 380000, 400000, 400000), CORE_DVFS("3d", 3, 1, KHZ, 247000, 285000, 351500, 400000, 400000, 400000, 400000), - CORE_DVFS("mpe", -1, 1, KHZ, 104500, 152000, 228000, 250000, 250000, 250000, 250000), + CORE_DVFS("mpe", 0, 1, KHZ, 104500, 152000, 228000, 300000, 300000, 300000, 300000), + CORE_DVFS("mpe", 1, 1, KHZ, 142500, 190000, 275500, 300000, 300000, 300000, 300000), + CORE_DVFS("mpe", 2, 1, KHZ, 190000, 237500, 300000, 300000, 300000, 300000, 300000), + CORE_DVFS("mpe", 3, 1, KHZ, 228000, 266000, 300000, 300000, 300000, 300000, 300000), + CORE_DVFS("vi", -1, 1, KHZ, 85000, 100000, 150000, 150000, 150000, 150000, 150000), CORE_DVFS("sclk", 0, 1, KHZ, 95000, 133000, 190000, 222500, 240000, 247000, 262000), |