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authorAmbresh K <ambresh@ti.com>2013-03-16 11:46:42 +0530
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2013-03-25 13:18:12 -0700
commit9ea03dec380208bfee015b25f253c2f58aba0071 (patch)
treedaae779fc72e6ab3157ae8191f63c738bb041ff9
parent0a5f19cf303ea9cc9bf89a42960a69db4ea3c35b (diff)
memory: emif: setup LP settings on freq update
Program the power management shadow register on freq update Else the concept of threshold frequencies dont really matter as the system always uses the performance mode timing for LP which is programmed in at init time. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Ambresh K <ambresh@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-rw-r--r--drivers/memory/emif.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/memory/emif.c b/drivers/memory/emif.c
index 897c39a8db86..bda11ebb25cd 100644
--- a/drivers/memory/emif.c
+++ b/drivers/memory/emif.c
@@ -819,6 +819,8 @@ static void setup_registers(struct emif_data *emif, struct emif_regs *regs)
writel(regs->sdram_tim2_shdw, base + EMIF_SDRAM_TIMING_2_SHDW);
writel(regs->phy_ctrl_1_shdw, base + EMIF_DDR_PHY_CTRL_1_SHDW);
+ writel(regs->pwr_mgmt_ctrl_shdw,
+ base + EMIF_POWER_MANAGEMENT_CTRL_SHDW);
/* Settings specific for EMIF4D5 */
if (emif->plat_data->ip_rev != EMIF_4D5)