nitrogen6x: default lcd pins off until lcd used

2 files changed, 79 insertions, 28 deletions

diff --git a/arch/arm/mach-mx6/board-mx6_nitrogen6x.c b/arch/arm/mach-mx6/board-mx6_nitrogen6x.c
index dcc2c6cea9ee..dee6a9ea1141 100644
--- a/arch/arm/mach-mx6/board-mx6_nitrogen6x.c
+++ b/arch/arm/mach-mx6/board-mx6_nitrogen6x.c
@@ -875,10 +875,24 @@ static struct fsl_mxc_hdmi_core_platform_data hdmi_core_data = {
 	.disp_id = 1,
 };
 
+static void lcd_enable_pins(void)
+{
+	pr_info("%s\n", __func__);
+	IOMUX_SETUP(lcd_pads_enable);
+}
+
+static void lcd_disable_pins(void)
+{
+	pr_info("%s\n", __func__);
+	IOMUX_SETUP(lcd_pads_disable);
+}
+
 static struct fsl_mxc_lcd_platform_data lcdif_data = {
 	.ipu_id = 0,
 	.disp_id = 0,
 	.default_ifmt = IPU_PIX_FMT_RGB565,
+	.enable_pins = lcd_enable_pins,
+	.disable_pins = lcd_disable_pins,
 };
 
 static struct fsl_mxc_ldb_platform_data ldb_data = {
@@ -1250,6 +1264,7 @@ static void __init board_init(void)
 	int isn6 ;
 
 	IOMUX_SETUP(common_pads);
+	lcd_disable_pins();
 
 	isn6 = is_nitrogen6w();
 	if (isn6) {
diff --git a/arch/arm/mach-mx6/pads-mx6_nitrogen6x.h b/arch/arm/mach-mx6/pads-mx6_nitrogen6x.h
index 5d87d92a4760..e134020f78d5 100644
--- a/arch/arm/mach-mx6/pads-mx6_nitrogen6x.h
+++ b/arch/arm/mach-mx6/pads-mx6_nitrogen6x.h
@@ -223,36 +223,8 @@ static iomux_v3_cfg_t MX6NAME(common_pads)[] = {
 #endif
 
 	/* DISPLAY */
-	MX6PAD(DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
-	MX6PAD(DI0_PIN15__IPU1_DI0_PIN15),		/* DE */
-	MX6PAD(DI0_PIN2__IPU1_DI0_PIN2),		/* HSync */
-	MX6PAD(DI0_PIN3__IPU1_DI0_PIN3),		/* VSync */
 	NEW_PAD_CTRL(MX6PAD(DI0_PIN4__GPIO_4_20),
 		     WEAK_PULLUP),			/* I2C Touch IRQ */
-	MX6PAD(DISP0_DAT0__IPU1_DISP0_DAT_0),
-	MX6PAD(DISP0_DAT1__IPU1_DISP0_DAT_1),
-	MX6PAD(DISP0_DAT2__IPU1_DISP0_DAT_2),
-	MX6PAD(DISP0_DAT3__IPU1_DISP0_DAT_3),
-	MX6PAD(DISP0_DAT4__IPU1_DISP0_DAT_4),
-	MX6PAD(DISP0_DAT5__IPU1_DISP0_DAT_5),
-	MX6PAD(DISP0_DAT6__IPU1_DISP0_DAT_6),
-	MX6PAD(DISP0_DAT7__IPU1_DISP0_DAT_7),
-	MX6PAD(DISP0_DAT8__IPU1_DISP0_DAT_8),
-	MX6PAD(DISP0_DAT9__IPU1_DISP0_DAT_9),
-	MX6PAD(DISP0_DAT10__IPU1_DISP0_DAT_10),
-	MX6PAD(DISP0_DAT11__IPU1_DISP0_DAT_11),
-	MX6PAD(DISP0_DAT12__IPU1_DISP0_DAT_12),
-	MX6PAD(DISP0_DAT13__IPU1_DISP0_DAT_13),
-	MX6PAD(DISP0_DAT14__IPU1_DISP0_DAT_14),
-	MX6PAD(DISP0_DAT15__IPU1_DISP0_DAT_15),
-	MX6PAD(DISP0_DAT16__IPU1_DISP0_DAT_16),
-	MX6PAD(DISP0_DAT17__IPU1_DISP0_DAT_17),
-	MX6PAD(DISP0_DAT18__IPU1_DISP0_DAT_18),
-	MX6PAD(DISP0_DAT19__IPU1_DISP0_DAT_19),
-	MX6PAD(DISP0_DAT20__IPU1_DISP0_DAT_20),
-	MX6PAD(DISP0_DAT21__IPU1_DISP0_DAT_21),
-	MX6PAD(DISP0_DAT22__IPU1_DISP0_DAT_22),
-	MX6PAD(DISP0_DAT23__IPU1_DISP0_DAT_23),
 	MX6PAD(GPIO_7__GPIO_1_7),		/* J7 - Display Connector GP */
 	MX6PAD(GPIO_9__GPIO_1_9),		/* J7 - Display Connector GP */
 	MX6PAD(NANDF_D0__GPIO_2_0),		/* J6 - LVDS Display contrast */
@@ -323,6 +295,70 @@ static iomux_v3_cfg_t MX6NAME(common_pads)[] = {
 	0
 };
 
+static iomux_v3_cfg_t MX6NAME(lcd_pads_enable)[] = {
+	MX6PAD(DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
+	MX6PAD(DI0_PIN15__IPU1_DI0_PIN15),		/* DE */
+	MX6PAD(DI0_PIN2__IPU1_DI0_PIN2),		/* HSync */
+	MX6PAD(DI0_PIN3__IPU1_DI0_PIN3),		/* VSync */
+	MX6PAD(DISP0_DAT0__IPU1_DISP0_DAT_0),
+	MX6PAD(DISP0_DAT1__IPU1_DISP0_DAT_1),
+	MX6PAD(DISP0_DAT2__IPU1_DISP0_DAT_2),
+	MX6PAD(DISP0_DAT3__IPU1_DISP0_DAT_3),
+	MX6PAD(DISP0_DAT4__IPU1_DISP0_DAT_4),
+	MX6PAD(DISP0_DAT5__IPU1_DISP0_DAT_5),
+	MX6PAD(DISP0_DAT6__IPU1_DISP0_DAT_6),
+	MX6PAD(DISP0_DAT7__IPU1_DISP0_DAT_7),
+	MX6PAD(DISP0_DAT8__IPU1_DISP0_DAT_8),
+	MX6PAD(DISP0_DAT9__IPU1_DISP0_DAT_9),
+	MX6PAD(DISP0_DAT10__IPU1_DISP0_DAT_10),
+	MX6PAD(DISP0_DAT11__IPU1_DISP0_DAT_11),
+	MX6PAD(DISP0_DAT12__IPU1_DISP0_DAT_12),
+	MX6PAD(DISP0_DAT13__IPU1_DISP0_DAT_13),
+	MX6PAD(DISP0_DAT14__IPU1_DISP0_DAT_14),
+	MX6PAD(DISP0_DAT15__IPU1_DISP0_DAT_15),
+	MX6PAD(DISP0_DAT16__IPU1_DISP0_DAT_16),
+	MX6PAD(DISP0_DAT17__IPU1_DISP0_DAT_17),
+	MX6PAD(DISP0_DAT18__IPU1_DISP0_DAT_18),
+	MX6PAD(DISP0_DAT19__IPU1_DISP0_DAT_19),
+	MX6PAD(DISP0_DAT20__IPU1_DISP0_DAT_20),
+	MX6PAD(DISP0_DAT21__IPU1_DISP0_DAT_21),
+	MX6PAD(DISP0_DAT22__IPU1_DISP0_DAT_22),
+	MX6PAD(DISP0_DAT23__IPU1_DISP0_DAT_23),
+	0
+};
+
+static iomux_v3_cfg_t MX6NAME(lcd_pads_disable)[] = {
+	MX6PAD(DI0_DISP_CLK__GPIO_4_16),
+	MX6PAD(DI0_PIN15__GPIO_4_17),			/* DE */
+	MX6PAD(DI0_PIN2__GPIO_4_18),			/* HSync */
+	MX6PAD(DI0_PIN3__GPIO_4_19),			/* VSync */
+	MX6PAD(DISP0_DAT0__GPIO_4_21),
+	MX6PAD(DISP0_DAT1__GPIO_4_22),
+	MX6PAD(DISP0_DAT2__GPIO_4_23),
+	MX6PAD(DISP0_DAT3__GPIO_4_24),
+	MX6PAD(DISP0_DAT4__GPIO_4_25),
+	MX6PAD(DISP0_DAT5__GPIO_4_26),
+	MX6PAD(DISP0_DAT6__GPIO_4_27),
+	MX6PAD(DISP0_DAT7__GPIO_4_28),
+	MX6PAD(DISP0_DAT8__GPIO_4_29),
+	MX6PAD(DISP0_DAT9__GPIO_4_30),
+	MX6PAD(DISP0_DAT10__GPIO_4_31),
+	MX6PAD(DISP0_DAT11__GPIO_5_5),
+	MX6PAD(DISP0_DAT12__GPIO_5_6),
+	MX6PAD(DISP0_DAT13__GPIO_5_7),
+	MX6PAD(DISP0_DAT14__GPIO_5_8),
+	MX6PAD(DISP0_DAT15__GPIO_5_9),
+	MX6PAD(DISP0_DAT16__GPIO_5_10),
+	MX6PAD(DISP0_DAT17__GPIO_5_11),
+	MX6PAD(DISP0_DAT18__GPIO_5_12),
+	MX6PAD(DISP0_DAT19__GPIO_5_13),
+	MX6PAD(DISP0_DAT20__GPIO_5_14),
+	MX6PAD(DISP0_DAT21__GPIO_5_15),
+	MX6PAD(DISP0_DAT22__GPIO_5_16),
+	MX6PAD(DISP0_DAT23__GPIO_5_17),
+	0
+};
+
 #if defined(CONFIG_MXC_CAMERA_OV5640_MIPI) || defined(CONFIG_MXC_CAMERA_OV5640_MIPI_MODULE)
 static iomux_v3_cfg_t MX6NAME(mipi_pads)[] = {
 	MX6PAD(NANDF_WP_B__GPIO_6_9),		/* J16 - MIPI Powerdown - Nitrogen6x, SOM is NC */