diff options
author | Eric Nelson <eric.nelson@boundarydevices.com> | 2013-12-12 15:52:35 -0700 |
---|---|---|
committer | Eric Nelson <eric.nelson@boundarydevices.com> | 2013-12-12 15:52:35 -0700 |
commit | 54317510c21cc8bfe99bfacd70469f0a6439fbd1 (patch) | |
tree | 98e9540c08e836d74ede848ca12c3698e4d1245a | |
parent | 86d0d5f17415ce2a92976aee03669e047dc5e58a (diff) | |
parent | 79a497e6d8f19e78a797e3cc86021adc0734bbd4 (diff) |
Merge branch 'boundary-imx_3.0.35_4.1.0' of github.com:boundarydevices/linux-imx6 into boundary-imx_3.0.35_4.1.0
-rw-r--r-- | arch/arm/mach-mx6/Kconfig | 33 | ||||
-rw-r--r-- | arch/arm/mach-mx6/Makefile | 1 | ||||
-rw-r--r-- | arch/arm/mach-mx6/board-mx6_r.c | 967 | ||||
-rw-r--r-- | arch/arm/mach-mx6/pads-mx6_r.h | 330 | ||||
-rw-r--r-- | arch/arm/tools/mach-types | 1 | ||||
-rw-r--r-- | drivers/rtc/rtc-isl1208.c | 4 | ||||
-rw-r--r-- | drivers/video/mxc/mxc_lcdif.c | 9 |
7 files changed, 1343 insertions, 2 deletions
diff --git a/arch/arm/mach-mx6/Kconfig b/arch/arm/mach-mx6/Kconfig index d7b275f0cb78..9f4502807023 100644 --- a/arch/arm/mach-mx6/Kconfig +++ b/arch/arm/mach-mx6/Kconfig @@ -220,6 +220,39 @@ config MACH_MX6Q_SABRELITE Include support for i.MX 6Quad SABRE Lite platform. This includes specific configurations for the board and its peripherals. +config MACH_MX6_R + bool "Support i.MX 6Quad R platform" + select ARCH_MX6Q + select SOC_IMX6Q + select IMX_HAVE_PLATFORM_IMX_UART + select IMX_HAVE_PLATFORM_DMA + select IMX_HAVE_PLATFORM_GPMI_NFC + select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX + select IMX_HAVE_PLATFORM_SPI_IMX + select IMX_HAVE_PLATFORM_IMX_I2C + select IMX_HAVE_PLATFORM_VIV_GPU + select IMX_HAVE_PLATFORM_IMX_VPU + select IMX_HAVE_PLATFORM_IMX_SSI + select IMX_HAVE_PLATFORM_IMX_ANATOP_THERMAL + select IMX_HAVE_PLATFORM_FSL_USB2_UDC + select IMX_HAVE_PLATFORM_MXC_EHCI + select IMX_HAVE_PLATFORM_FSL_OTG + select IMX_HAVE_PLATFORM_FSL_USB_WAKEUP + select IMX_HAVE_PLATFORM_AHCI + select IMX_HAVE_PLATFORM_IMX_OCOTP + select IMX_HAVE_PLATFORM_IMX_VIIM + select IMX_HAVE_PLATFORM_IMX2_WDT + select IMX_HAVE_PLATFORM_IMX_SNVS_RTC + select IMX_HAVE_PLATFORM_IMX_PM + select IMX_HAVE_PLATFORM_MXC_HDMI + select IMX_HAVE_PLATFORM_IMX_ASRC + select IMX_HAVE_PLATFORM_IMX_DVFS + select IMX_HAVE_PLATFORM_IMX_MIPI_CSI2 + select IMX_HAVE_PLATFORM_PERFMON + help + Include support for i.MX 6Quad R platform. This includes specific + configurations for the board and its peripherals. + config MACH_MX6_S bool "Support i.MX 6Quad S board" select ARCH_MX6Q diff --git a/arch/arm/mach-mx6/Makefile b/arch/arm/mach-mx6/Makefile index e2ec80a665fc..2827e931dac3 100644 --- a/arch/arm/mach-mx6/Makefile +++ b/arch/arm/mach-mx6/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_MACH_MX6SL_ARM2) += board-mx6sl_arm2.o mx6sl_arm2_pmic_pfuze100.o obj-$(CONFIG_MACH_MX6SL_EVK) += board-mx6sl_evk.o mx6sl_evk_pmic_pfuze100.o obj-$(CONFIG_MACH_MX6Q_SABRELITE) += board-mx6q_sabrelite.o obj-$(CONFIG_MACH_MX6_NITROGEN6X) += board-mx6_nitrogen6x.o +obj-$(CONFIG_MACH_MX6_R) += board-mx6_r.o obj-$(CONFIG_MACH_MX6_UTC) += board-mx6_utc.o obj-$(CONFIG_MACH_MX6_S) += board-mx6_s.o obj-$(CONFIG_MACH_MX6_OC) += board-mx6_oc.o diff --git a/arch/arm/mach-mx6/board-mx6_r.c b/arch/arm/mach-mx6/board-mx6_r.c new file mode 100644 index 000000000000..70b0954afd11 --- /dev/null +++ b/arch/arm/mach-mx6/board-mx6_r.c @@ -0,0 +1,967 @@ +/* + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/types.h> +#include <linux/sched.h> +#include <linux/delay.h> +#include <linux/pm.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/init.h> +#include <linux/input.h> +#include <linux/nodemask.h> +#include <linux/clk.h> +#include <linux/platform_device.h> +#include <linux/fsl_devices.h> +#include <linux/spi/spi.h> +#include <linux/spi/flash.h> +#include <linux/i2c.h> +#include <linux/i2c/pca953x.h> +#include <linux/ata.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/map.h> +#include <linux/mtd/partitions.h> +#include <linux/regulator/consumer.h> +#include <linux/pmic_external.h> +#include <linux/pmic_status.h> +#include <linux/ipu.h> +#include <linux/mxcfb.h> +#include <linux/pwm.h> +#include <linux/pwm_backlight.h> +#include <linux/fec.h> +#include <linux/memblock.h> +#include <linux/micrel_phy.h> +#include <linux/gpio.h> +#include <linux/etherdevice.h> +#include <linux/regulator/anatop-regulator.h> +#include <linux/regulator/consumer.h> +#include <linux/regulator/machine.h> +#include <linux/regulator/fixed.h> + +#include <mach/common.h> +#include <mach/hardware.h> +#include <mach/mxc_dvfs.h> +#include <mach/memory.h> +#include <mach/iomux-mx6q.h> +#include <mach/iomux-mx6dl.h> +#include <mach/imx_rfkill.h> +#include <mach/imx-uart.h> +#include <mach/viv_gpu.h> +#include <mach/ahci_sata.h> +#include <mach/ipu-v3.h> +#include <mach/mxc_hdmi.h> +#include <mach/mxc_asrc.h> +#include <linux/i2c/tsc2007.h> +#include <linux/wl12xx.h> + +#include <asm/irq.h> +#include <asm/setup.h> +#include <asm/mach-types.h> +#include <asm/mach/arch.h> +#include <asm/mach/time.h> + +#include "usb.h" +#include "devices-imx6q.h" +#include "crm_regs.h" +#include "cpu_op-mx6.h" + +#define GP_SD3_CD IMX_GPIO_NR(7, 0) +#define GP_ECSPI1_CS1 IMX_GPIO_NR(3, 19) +#define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22) +#define GP_CAP_TCH_INT1 IMX_GPIO_NR(1, 9) +#define GP_EMMC_RESET IMX_GPIO_NR(2, 23) +#define GP_CAM_POWER_DOWN IMX_GPIO_NR(5, 21) +#define GP_CAM_RESET IMX_GPIO_NR(5, 20) + +#define GP_WL1271_WL_IRQ IMX_GPIO_NR(6, 14) +#define GP_WL1271_WL_EN IMX_GPIO_NR(6, 15) +#define GP_WL1271_BT_EN IMX_GPIO_NR(6, 16) + +#include "pads-mx6_r.h" +#define FOR_DL_SOLO +#include "pads-mx6_r.h" + +void __init early_console_setup(unsigned long base, struct clk *clk); +static struct clk *sata_clk; + +extern char *gp_reg_id; +extern char *soc_reg_id; +extern char *pu_reg_id; + +extern struct regulator *(*get_cpu_regulator)(void); +extern void (*put_cpu_regulator)(void); + +#define IOMUX_SETUP(pad_list) mxc_iomux_v3_setup_pads(mx6q_##pad_list, \ + mx6dl_solo_##pad_list) + +static int mxc_iomux_v3_setup_pads(iomux_v3_cfg_t *mx6q_pad_list, + iomux_v3_cfg_t *mx6dl_solo_pad_list) +{ + iomux_v3_cfg_t *p = cpu_is_mx6q() ? mx6q_pad_list : mx6dl_solo_pad_list; + int ret; + + while (*p) { + ret = mxc_iomux_v3_setup_pad(*p); + if (ret) + return ret; + p++; + } + return 0; +} + +enum sd_pad_mode { + SD_PAD_MODE_LOW_SPEED, + SD_PAD_MODE_MED_SPEED, + SD_PAD_MODE_HIGH_SPEED, +}; + +static int plt_sd_pad_change(unsigned int index, int clock) +{ + /* LOW speed is the default state of SD pads */ + static enum sd_pad_mode pad_mode = SD_PAD_MODE_LOW_SPEED; + int i = (index - 1) * SD_SPEED_CNT; + + if ((index < 1) || (index > 3)) { + printk(KERN_ERR "no such SD host controller index %d\n", index); + return -EINVAL; + } + + if (clock > 100000000) { + if (pad_mode == SD_PAD_MODE_HIGH_SPEED) + return 0; + pad_mode = SD_PAD_MODE_HIGH_SPEED; + i += _200MHZ; + } else if (clock > 52000000) { + if (pad_mode == SD_PAD_MODE_MED_SPEED) + return 0; + pad_mode = SD_PAD_MODE_MED_SPEED; + i += _100MHZ; + } else { + if (pad_mode == SD_PAD_MODE_LOW_SPEED) + return 0; + pad_mode = SD_PAD_MODE_LOW_SPEED; + i += _50MHZ; + } + return IOMUX_SETUP(sd_pads[i]); +} + +static void sdio_set_power(int on) +{ + pr_debug("%s:%s: set power(%d)\n", + __FILE__, __func__, on); + gpio_set_value(GP_WL1271_WL_EN,on); +} + +#ifdef CONFIG_WL12XX_PLATFORM_DATA +static struct esdhc_platform_data sd2_data = { + .always_present = 1, + .cd_gpio = -1, + .wp_gpio = -1, + .keep_power_at_suspend = 0, + .caps = MMC_CAP_POWER_OFF_CARD, + .platform_pad_change = plt_sd_pad_change, + .set_power = sdio_set_power, +}; +#endif + +static struct esdhc_platform_data sd3_data = { + .cd_gpio = GP_SD3_CD, + .wp_gpio = -1, + .keep_power_at_suspend = 1, + .platform_pad_change = plt_sd_pad_change, +}; + +static const struct esdhc_platform_data sd4_data __initconst = { + .cd_gpio = -1, + .wp_gpio = -1, + .always_present = 1, + .keep_power_at_suspend = 1, + .support_8bit = 1, + .platform_pad_change = plt_sd_pad_change, +}; + +static const struct anatop_thermal_platform_data + anatop_thermal_data __initconst = { + .name = "anatop_thermal", +}; + +static const struct imxuart_platform_data mx6_arm2_uart2_data __initconst = { + .flags = IMXUART_HAVE_RTSCTS, +}; + +static int spi_cs[] = { + GP_ECSPI1_CS1, +}; + +static const struct spi_imx_master spi_data __initconst = { + .chipselect = spi_cs, + .num_chipselect = ARRAY_SIZE(spi_cs), +}; + +#if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) +static struct mtd_partition spi_nor_partitions[] = { + { + .name = "bootloader", + .offset = 0, + .size = 768*1024, + }, + { + .name = "ubparams", + .offset = MTDPART_OFS_APPEND, + .size = 8*1024, + }, + { + .name = "unused", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct flash_platform_data spi_flash_data = { + .name = "m25p80", + .parts = spi_nor_partitions, + .nr_parts = ARRAY_SIZE(spi_nor_partitions), + .type = "sst25vf016b", +}; +#endif + +static struct spi_board_info spi_nor_device[] __initdata = { +#if defined(CONFIG_MTD_M25P80) + { + .modalias = "m25p80", + .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 0, + .chip_select = 0, + .platform_data = &spi_flash_data, + }, +#endif +}; + +static void spi_device_init(void) +{ + spi_register_board_info(spi_nor_device, + ARRAY_SIZE(spi_nor_device)); +} + +static struct clk *mipi_mclk; + +static int mipi_mclk_init(void) +{ + struct clk *clko; + struct clk *new_parent; + int rate; + + clko = clk_get(NULL, "clko_clk"); + if (IS_ERR(clko)) { + pr_err("can't get CLKO clock.\n"); + return PTR_ERR(clko); + } + new_parent = clk_get(NULL, "ahb"); + if (!IS_ERR(new_parent)) { + clk_set_parent(clko, new_parent); + clk_put(new_parent); + } + rate = clk_round_rate(clko, 22000000); + if (rate < 20000000 || rate > 27000000) { + pr_err("Error:mipi mclk freq %d out of range!\n", rate); + clk_put(clko); + return -1; + } + clk_set_rate(clko, rate); + mipi_mclk = clko; + return 0; +} + +static struct imxi2c_platform_data i2c_data = { + .bitrate = 100000, +}; + +static struct i2c_board_info mxc_i2c0_board_info[] __initdata = { + /* Battery pack - ND2034HD29 */ +}; + +static void camera_reset(int power_gp, int poweroff_level, int reset_gp) +{ + pr_info("%s: power_gp=0x%x, reset_gp=0x%x\n", + __func__, power_gp, reset_gp); + /* Camera power down */ + gpio_direction_output(power_gp, poweroff_level); + /* Camera reset */ + gpio_direction_output(reset_gp, 0); + msleep(1); + gpio_set_value(power_gp, poweroff_level ^ 1); + msleep(1); + gpio_set_value(reset_gp, 1); +} + + +static void ov5640_mipi_camera_io_init(void) +{ + IOMUX_SETUP(mipi_pads); + + pr_info("%s\n", __func__); + mipi_mclk_init(); + + camera_reset(GP_CAM_POWER_DOWN, 1, GP_CAM_RESET); +/* for mx6dl, mipi virtual channel 1 connect to csi 1*/ + if (cpu_is_mx6dl()) + mxc_iomux_set_gpr_register(13, 3, 3, 1); +} + +static void ov5640_mipi_camera_powerdown(int powerdown) +{ + if (!IS_ERR(mipi_mclk)) { + if (powerdown) { + clk_disable(mipi_mclk); + } else { + clk_enable(mipi_mclk); + } + } + pr_info("%s: powerdown=%d, power_gp=0x%x\n", + __func__, powerdown, IMX_GPIO_NR(6, 9)); + gpio_set_value(IMX_GPIO_NR(5, 21), powerdown ? 1 : 0); + if (!powerdown) + msleep(2); +} + +static struct fsl_mxc_camera_platform_data ov5640_mipi_data = { + .mclk = 22000000, + .csi = 0, + .io_init = ov5640_mipi_camera_io_init, + .pwdn = ov5640_mipi_camera_powerdown, +}; + +static struct i2c_board_info mxc_i2c1_board_info[] __initdata = { + { + I2C_BOARD_INFO("mxc_hdmi_i2c", 0x50), + }, + { + I2C_BOARD_INFO("ft5x06-ts", 0x38), + .irq = gpio_to_irq(GP_CAP_TCH_INT1), + }, + { + I2C_BOARD_INFO("ov5640_mipi", 0x3c), + .platform_data = (void *)&ov5640_mipi_data, + }, +}; + +static struct i2c_board_info mxc_i2c2_board_info[] __initdata = { + { + I2C_BOARD_INFO("isl1208", 0x6f), /* Real time clock */ + .irq = gpio_to_irq(IMX_GPIO_NR(6, 7)), /* NANDF_CLE */ + }, +}; + +static void usbotg_vbus(bool on) +{ + pr_info("%s: on=%d\n", __func__, on); + gpio_set_value(GP_USB_OTG_PWR, on ? 1 : 0); +} + +static void __init init_usb(void) +{ + imx_otg_base = MX6_IO_ADDRESS(MX6Q_USB_OTG_BASE_ADDR); + mxc_iomux_set_gpr_register(1, 13, 1, 1); /* GPIO1 USB_ID */ + + mx6_set_otghost_vbus_func(usbotg_vbus); +} + +/* HW Initialization, if return 0, initialization is successful. */ +static int init_sata(struct device *dev, void __iomem *addr) +{ + u32 tmpdata; + int ret = 0; + struct clk *clk; + + sata_clk = clk_get(dev, "imx_sata_clk"); + if (IS_ERR(sata_clk)) { + dev_err(dev, "no sata clock.\n"); + return PTR_ERR(sata_clk); + } + ret = clk_enable(sata_clk); + if (ret) { + dev_err(dev, "can't enable sata clock.\n"); + goto put_sata_clk; + } + + /* Set PHY Paremeters, two steps to configure the GPR13, + * one write for rest of parameters, mask of first write is 0x07FFFFFD, + * and the other one write for setting the mpll_clk_off_b + *.rx_eq_val_0(iomuxc_gpr13[26:24]), + *.los_lvl(iomuxc_gpr13[23:19]), + *.rx_dpll_mode_0(iomuxc_gpr13[18:16]), + *.sata_speed(iomuxc_gpr13[15]), + *.mpll_ss_en(iomuxc_gpr13[14]), + *.tx_atten_0(iomuxc_gpr13[13:11]), + *.tx_boost_0(iomuxc_gpr13[10:7]), + *.tx_lvl(iomuxc_gpr13[6:2]), + *.mpll_ck_off(iomuxc_gpr13[1]), + *.tx_edgerate_0(iomuxc_gpr13[0]), + */ + tmpdata = readl(IOMUXC_GPR13); + writel(((tmpdata & ~0x07FFFFFF) | 0x0593A044), IOMUXC_GPR13); + + /* enable SATA_PHY PLL */ + tmpdata = readl(IOMUXC_GPR13); + writel(((tmpdata & ~0x2) | 0x2), IOMUXC_GPR13); + + /* Get the AHB clock rate, and configure the TIMER1MS reg later */ + clk = clk_get(NULL, "ahb"); + if (IS_ERR(clk)) { + dev_err(dev, "no ahb clock.\n"); + ret = PTR_ERR(clk); + goto release_sata_clk; + } + tmpdata = clk_get_rate(clk) / 1000; + clk_put(clk); + + ret = sata_init(addr, tmpdata); + if (ret == 0) + return ret; + +release_sata_clk: + clk_disable(sata_clk); +put_sata_clk: + clk_put(sata_clk); + + return ret; +} + +static void exit_sata(struct device *dev) +{ + clk_disable(sata_clk); + clk_put(sata_clk); +} + +static struct ahci_platform_data sata_data = { + .init = init_sata, + .exit = exit_sata, +}; + +static struct viv_gpu_platform_data imx6_gpu_pdata __initdata = { + .reserved_mem_size = SZ_128M, +}; + +static struct imx_asrc_platform_data imx_asrc_data = { + .channel_bits = 4, + .clk_map_ver = 2, +}; + +static struct ipuv3_fb_platform_data fb_data[] = { + { /*fb0*/ + .disp_dev = "lcd", + .interface_pix_fmt = IPU_PIX_FMT_RGB565, + .mode_str = "LB043", + .default_bpp = 32, + .int_clk = false, + }, +}; + +static void hdmi_init(int ipu_id, int disp_id) +{ + int hdmi_mux_setting; + + if ((ipu_id > 1) || (ipu_id < 0)) { + pr_err("Invalid IPU select for HDMI: %d. Set to 0\n", ipu_id); + ipu_id = 0; + } + + if ((disp_id > 1) || (disp_id < 0)) { + pr_err("Invalid DI select for HDMI: %d. Set to 0\n", disp_id); + disp_id = 0; + } + + /* Configure the connection between IPU1/2 and HDMI */ + hdmi_mux_setting = 2*ipu_id + disp_id; + + /* GPR3, bits 2-3 = HDMI_MUX_CTL */ + mxc_iomux_set_gpr_register(3, 2, 2, hdmi_mux_setting); + + /* Set HDMI event as SDMA event2 while Chip version later than TO1.2 */ + if ((mx6q_revision() > IMX_CHIP_REVISION_1_1)) + mxc_iomux_set_gpr_register(0, 0, 1, 1); +} + +/* On mx6x sbarelite board i2c2 iomux with hdmi ddc, + * the pins default work at i2c2 function, + when hdcp enable, the pins should work at ddc function */ + +static void hdmi_enable_ddc_pin(void) +{ + IOMUX_SETUP(hdmi_ddc_pads); +} + +static void hdmi_disable_ddc_pin(void) +{ + IOMUX_SETUP(i2c2_pads); +} + +static struct fsl_mxc_hdmi_platform_data hdmi_data = { + .init = hdmi_init, + .enable_pins = hdmi_enable_ddc_pin, + .disable_pins = hdmi_disable_ddc_pin, +}; + +static struct fsl_mxc_hdmi_core_platform_data hdmi_core_data = { + .ipu_id = 0, + .disp_id = 1, +}; + +static void lcd_enable_pins(void) +{ + pr_info("%s\n", __func__); + IOMUX_SETUP(lcd_pads_enable); +} + +static void lcd_disable_pins(void) +{ + pr_info("%s\n", __func__); + IOMUX_SETUP(lcd_pads_disable); +} + +static struct fsl_mxc_lcd_platform_data lcdif_data = { + .ipu_id = 0, + .disp_id = 0, + .default_ifmt = IPU_PIX_FMT_RGB565, + .enable_pins = lcd_enable_pins, + .disable_pins = lcd_disable_pins, +}; + +static struct imx_ipuv3_platform_data ipu_data[] = { + { + .rev = 4, + .csi_clk[0] = "clko2_clk", + }, { + .rev = 4, + .csi_clk[0] = "clko2_clk", + }, +}; + +static struct fsl_mxc_capture_platform_data capture_data[] = { + { + .ipu = 0, + .csi = 0, + .mclk_source = 0, + .is_mipi = 1, + }, +}; + + +static void suspend_enter(void) +{ + /* suspend preparation */ +} + +static void suspend_exit(void) +{ + /* resume restore */ +} +static const struct pm_platform_data pm_data __initconst = { + .name = "imx_pm", + .suspend_enter = suspend_enter, + .suspend_exit = suspend_exit, +}; + +#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake) \ +{ \ + .gpio = gpio_num, \ + .type = EV_KEY, \ + .code = ev_code, \ + .active_low = act_low, \ + .desc = "btn " descr, \ + .wakeup = wake, \ +} + +static struct gpio_keys_button buttons[] = { + GPIO_BUTTON(IMX_GPIO_NR(6, 11), KEY_POWER, 1, "key-power", 1), + GPIO_BUTTON(IMX_GPIO_NR(3, 0), KEY_MENU, 1, "key-memu", 0), + GPIO_BUTTON(IMX_GPIO_NR(3, 1), KEY_HOME, 1, "key-home", 0), + GPIO_BUTTON(IMX_GPIO_NR(3, 2), KEY_BACK, 1, "key-back", 0), + GPIO_BUTTON(IMX_GPIO_NR(3, 3), KEY_VOLUMEUP, 1, "volume-up", 0), + GPIO_BUTTON(IMX_GPIO_NR(4, 5), KEY_VOLUMEDOWN, 1, "volume-down", 0), +}; + +#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) +static struct gpio_keys_platform_data button_data = { + .buttons = buttons, + .nbuttons = ARRAY_SIZE(buttons), +}; + +static struct platform_device button_device = { + .name = "gpio-keys", + .id = -1, + .num_resources = 0, + .dev = { + .platform_data = &button_data, + } +}; + +static void __init add_device_buttons(void) +{ + platform_device_register(&button_device); +} +#else +static void __init add_device_buttons(void) +{ + int i; + for (i=0; i < ARRAY_SIZE(buttons);i++) { + int gpio = buttons[i].gpio; + pr_debug("%s: exporting gpio %d\n", __func__, gpio); + gpio_export(gpio,1); + } +} +#endif + +#ifdef CONFIG_WL12XX_PLATFORM_DATA +static void wl1271_set_power(bool enable) +{ + if (0 == enable) { + gpio_set_value(GP_WL1271_WL_EN, 0); /* momentarily disable */ + mdelay(2); + gpio_set_value(GP_WL1271_WL_EN, 1); + } +} + +struct wl12xx_platform_data n6q_wlan_data __initdata = { + .irq = gpio_to_irq(GP_WL1271_WL_IRQ), + .board_ref_clock = WL12XX_REFCLOCK_38, /* 38.4 MHz */ + .set_power = wl1271_set_power, +}; + +static struct regulator_consumer_supply n6q_vwl1271_consumers[] = { + REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.1"), +}; + +static struct regulator_init_data n6q_vwl1271_init = { + .constraints = { + .name = "VDD_1.8V", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(n6q_vwl1271_consumers), + .consumer_supplies = n6q_vwl1271_consumers, +}; + +static struct fixed_voltage_config n6q_vwl1271_reg_config = { + .supply_name = "vwl1271", + .microvolts = 1800000, /* 1.80V */ + .gpio = GP_WL1271_WL_EN, + .startup_delay = 70000, /* 70ms */ + .enable_high = 1, + .enabled_at_boot = 0, + .init_data = &n6q_vwl1271_init, +}; + +static struct platform_device n6q_vwl1271_reg_devices = { + .name = "reg-fixed-voltage", + .id = 4, + .dev = { + .platform_data = &n6q_vwl1271_reg_config, + }, +}; +#endif + +static struct regulator_consumer_supply vmmc_consumers[] = { + REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.2"), + REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.3"), +}; + +static struct regulator_init_data vmmc_init = { + .num_consumer_supplies = ARRAY_SIZE(vmmc_consumers), + .consumer_supplies = vmmc_consumers, +}; + +static struct fixed_voltage_config vmmc_reg_config = { + .supply_name = "vmmc", + .microvolts = 3300000, + .gpio = -1, + .init_data = &vmmc_init, +}; + +static struct platform_device vmmc_reg_devices = { + .name = "reg-fixed-voltage", + .id = 3, + .dev = { + .platform_data = &vmmc_reg_config, + }, +}; + +/* PWM1_PWMO: backlight control on DRGB connector */ +static struct platform_pwm_backlight_data pwm1_backlight_data = { + .pwm_id = 0, /* pin SD1_DATA3 - PWM1 */ + .max_brightness = 256, + .dft_brightness = 256, + .pwm_period_ns = 1000000000/32768, +}; + +static struct mxc_dvfs_platform_data dvfscore_data = { + .reg_id = "cpu_vddgp", + .soc_id = "cpu_vddsoc", + .pu_id = "cpu_vddvpu", + .clk1_id = "cpu_clk", + .clk2_id = "gpc_dvfs_clk", + .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET, + .ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET, + .ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET, + .ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET, + .prediv_mask = 0x1F800, + .prediv_offset = 11, + .prediv_val = 3, + .div3ck_mask = 0xE0000000, + .div3ck_offset = 29, + .div3ck_val = 2, + .emac_val = 0x08, + .upthr_val = 25, + .dnthr_val = 9, + .pncthr_val = 33, + .upcnt_val = 10, + .dncnt_val = 10, + .delay_time = 80, +}; + +static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, + char **cmdline, struct meminfo *mi) +{ +} + +static struct mipi_csi2_platform_data mipi_csi2_pdata = { + .ipu_id = 0, + .csi_id = 0, + .v_channel = 0, + .lanes = 2, + .dphy_clk = "mipi_pllref_clk", + .pixel_clk = "emi_clk", +}; + +static const struct imx_pcie_platform_data pcie_data __initconst = { + .pcie_pwr_en = -EINVAL, + .pcie_rst = -EINVAL, + .pcie_wake_up = -EINVAL, + .pcie_dis = -EINVAL, +}; + +#define GPIOF_HIGH GPIOF_OUT_INIT_HIGH + +struct gpio r_gpios[] __initdata = { + {.label = "main_power_en", .gpio = IMX_GPIO_NR(1, 16), .flags = GPIOF_HIGH}, + {.label = "cam-pwdn", .gpio = GP_CAM_POWER_DOWN, .flags = GPIOF_HIGH}, + {.label = "cam-reset", .gpio = GP_CAM_RESET, .flags = 0}, + {.label = "touch wake" , .gpio = IMX_GPIO_NR(2, 3), .flags = GPIOF_HIGH}, + {.label = "touch reset" , .gpio = IMX_GPIO_NR(2, 4), .flags = GPIOF_HIGH}, + {.label = "emmc_reset" , .gpio = GP_EMMC_RESET, .flags = 0}, + {.label = "wl1271_int", .gpio = GP_WL1271_WL_IRQ, .flags = GPIOF_DIR_IN}, + {.label = "wl1271_bt_en", .gpio = GP_WL1271_BT_EN, .flags = 0}, + {.label = "wl1271_wl_en", .gpio = GP_WL1271_WL_EN, .flags = 0}, + {.label = "usb-pwr", .gpio = GP_USB_OTG_PWR, .flags = 0}, +}; + +static int bt_power_change(int status) +{ + gpio_set_value(GP_WL1271_BT_EN, status ? 1 : 0); + return 0; +} + +static struct platform_device mxc_bt_rfkill = { + .name = "mxc_bt_rfkill", +}; + +static struct imx_bt_rfkill_platform_data mxc_bt_rfkill_data = { + .power_change = bt_power_change, +}; + +/*! + * Board specific initialization. + */ +static void __init board_init(void) +{ + int i, j; + int ret; + + ret = gpio_request_array(r_gpios, + ARRAY_SIZE(r_gpios)); + + IOMUX_SETUP(common_pads); + lcd_disable_pins(); + + if (ret) { + printk(KERN_ERR "%s gpio_request_array failed(" + "%d) for r_gpios\n", __func__, ret); + } + + printk(KERN_ERR "------------ Board type mx6_r\n"); + +#ifdef CONFIG_FEC_1588 + /* Set GPIO_16 input for IEEE-1588 ts_clk and RMII reference clock + * For MX6 GPR1 bit21 meaning: + * Bit21: 0 - GPIO_16 pad output + * 1 - GPIO_16 pad input + */ + mxc_iomux_set_gpr_register(1, 21, 1, 1); +#endif + + gp_reg_id = dvfscore_data.reg_id; + soc_reg_id = dvfscore_data.soc_id; + pu_reg_id = dvfscore_data.pu_id; + + imx6q_add_imx_uart(0, NULL); + imx6q_add_imx_uart(1, NULL); + imx6q_add_imx_uart(2, &mx6_arm2_uart2_data); + + imx6q_add_mxc_hdmi_core(&hdmi_core_data); + + imx6q_add_ipuv3(0, &ipu_data[0]); + if (cpu_is_mx6q()) { + imx6q_add_ipuv3(1, &ipu_data[1]); + } + j = ARRAY_SIZE(fb_data); + for (i = 0; i < j; i++) + imx6q_add_ipuv3fb(i, &fb_data[i]); + + imx6q_add_vdoa(); + imx6q_add_lcdif(&lcdif_data); + imx6q_add_v4l2_output(0); + + for (i = 0; i < ARRAY_SIZE(capture_data); i++) { + if (!cpu_is_mx6q()) + capture_data[i].ipu = 0; + imx6q_add_v4l2_capture(i, &capture_data[i]); + } + + imx6q_add_mipi_csi2(&mipi_csi2_pdata); + imx6q_add_imx_snvs_rtc(); + + imx6q_add_imx_i2c(0, &i2c_data); + imx6q_add_imx_i2c(1, &i2c_data); + imx6q_add_imx_i2c(2, &i2c_data); + + i2c_register_board_info(0, mxc_i2c0_board_info, + ARRAY_SIZE(mxc_i2c0_board_info)); + i2c_register_board_info(1, mxc_i2c1_board_info, + ARRAY_SIZE(mxc_i2c1_board_info)); + i2c_register_board_info(2, mxc_i2c2_board_info, + ARRAY_SIZE(mxc_i2c2_board_info)); + + /* SPI */ + imx6q_add_ecspi(0, &spi_data); + spi_device_init(); + + imx6q_add_mxc_hdmi(&hdmi_data); + + imx6q_add_anatop_thermal_imx(1, &anatop_thermal_data); + imx6q_add_pm_imx(0, &pm_data); + imx6q_add_sdhci_usdhc_imx(2, &sd3_data); + imx6q_add_sdhci_usdhc_imx(3, &sd4_data); + imx_add_viv_gpu(&imx6_gpu_data, &imx6_gpu_pdata); + init_usb(); + if (cpu_is_mx6q()) + imx6q_add_ahci(0, &sata_data); + imx6q_add_vpu(); + platform_device_register(&vmmc_reg_devices); + imx_asrc_data.asrc_core_clk = clk_get(NULL, "asrc_clk"); + imx_asrc_data.asrc_audio_clk = clk_get(NULL, "asrc_serial_clk"); + imx6q_add_asrc(&imx_asrc_data); + + imx6q_add_mxc_pwm(0); + imx6q_add_mxc_pwm(1); + + imx6q_add_mxc_pwm_backlight(0, &pwm1_backlight_data); + + imx6q_add_otp(); + imx6q_add_viim(); + imx6q_add_imx2_wdt(0, NULL); + imx6q_add_dma(); + + imx6q_add_dvfs_core(&dvfscore_data); + + add_device_buttons(); + + imx6q_add_hdmi_soc(); + imx6q_add_hdmi_soc_dai(); + + imx6q_add_busfreq(); + +#ifdef CONFIG_WL12XX_PLATFORM_DATA + imx6q_add_sdhci_usdhc_imx(1, &sd2_data); + /* WL12xx WLAN Init */ + if (wl12xx_set_platform_data(&n6q_wlan_data)) + pr_err("error setting wl12xx data\n"); + platform_device_register(&n6q_vwl1271_reg_devices); + + gpio_set_value(GP_WL1271_WL_EN, 1); /* momentarily enable */ + gpio_set_value(GP_WL1271_BT_EN, 1); + mdelay(2); + gpio_set_value(GP_WL1271_WL_EN, 0); + gpio_set_value(GP_WL1271_BT_EN, 0); + + gpio_free(GP_WL1271_WL_EN); + gpio_free(GP_WL1271_BT_EN); + mdelay(1); +#endif + + mxc_register_device(&mxc_bt_rfkill, &mxc_bt_rfkill_data); + gpio_set_value(GP_EMMC_RESET, 1); /* Release EMMC reset */ + imx6_add_armpmu(); + imx6q_add_perfmon(0); + imx6q_add_perfmon(1); + imx6q_add_perfmon(2); +} + +extern void __iomem *twd_base; +static void __init timer_init(void) +{ + struct clk *uart_clk; +#ifdef CONFIG_LOCAL_TIMERS + twd_base = ioremap(LOCAL_TWD_ADDR, SZ_256); + BUG_ON(!twd_base); +#endif + mx6_clocks_init(32768, 24000000, 0, 0); + + uart_clk = clk_get_sys("imx-uart.0", NULL); + early_console_setup(UART2_BASE_ADDR, uart_clk); +} + +static struct sys_timer timer __initdata = { + .init = timer_init, +}; + +static void __init reserve(void) +{ +#if defined(CONFIG_MXC_GPU_VIV) || defined(CONFIG_MXC_GPU_VIV_MODULE) + phys_addr_t phys; + + if (imx6_gpu_pdata.reserved_mem_size) { + phys = memblock_alloc_base(imx6_gpu_pdata.reserved_mem_size, + SZ_4K, SZ_1G); + memblock_remove(phys, imx6_gpu_pdata.reserved_mem_size); + imx6_gpu_pdata.reserved_mem_base = phys; + } +#endif +} + +/* + * initialize __mach_desc_MX6Q_SABRELITE data structure. + */ +MACHINE_START(MX6_R, "Boundary Devices Nitrogen6X/SABRE Lite Board") + /* Maintainer: Boundary Devices */ + .boot_params = MX6_PHYS_OFFSET + 0x100, + .fixup = fixup_mxc_board, + .map_io = mx6_map_io, + .init_irq = mx6_init_irq, + .init_machine = board_init, + .timer = &timer, + .reserve = reserve, +MACHINE_END diff --git a/arch/arm/mach-mx6/pads-mx6_r.h b/arch/arm/mach-mx6/pads-mx6_r.h new file mode 100644 index 000000000000..4f19512cadc4 --- /dev/null +++ b/arch/arm/mach-mx6/pads-mx6_r.h @@ -0,0 +1,330 @@ +#undef MX6PAD +#undef MX6NAME +#undef MX6 + +#ifdef FOR_DL_SOLO +#define MX6(a) MX6DL_##a +#define MX6PAD(a) MX6DL_PAD_##a +#define MX6NAME(a) mx6dl_solo_##a +#else +#define MX6(a) MX6Q_##a +#define MX6PAD(a) MX6Q_PAD_##a +#define MX6NAME(a) mx6q_##a +#endif + +#define WEAK_PULLUP (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm) +#define ISL1208_IRQ_PADCFG (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) + +#define N6_IRQ_PADCFG (PAD_CTL_PUE | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) +#define N6_EN_PADCFG (PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) + +#define PAD_CTL_PIS(pull, impede, speed) (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_##pull | PAD_CTL_SPEED_##speed | \ + PAD_CTL_DSE_##impede | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define MX6Q_USDHC_PAD_CTRL_22KPU_34OHM_50MHZ PAD_CTL_PIS(22K_UP, 34ohm, LOW) +#define MX6Q_USDHC_PAD_CTRL_22KPU_40OHM_50MHZ PAD_CTL_PIS(22K_UP, 40ohm, LOW) +#define MX6Q_USDHC_PAD_CTRL_22KPU_48OHM_50MHZ PAD_CTL_PIS(22K_UP, 48ohm, LOW) +#define MX6Q_USDHC_PAD_CTRL_22KPU_60OHM_50MHZ PAD_CTL_PIS(22K_UP, 60ohm, LOW) +#define MX6Q_USDHC_PAD_CTRL_22KPU_80OHM_50MHZ PAD_CTL_PIS(22K_UP, 80ohm, LOW) +#define MX6Q_USDHC_PAD_CTRL_22KPU_120OHM_50MHZ PAD_CTL_PIS(22K_UP, 120ohm, LOW) +#define MX6Q_USDHC_PAD_CTRL_47KPU_34OHM_50MHZ PAD_CTL_PIS(47K_UP, 34ohm, LOW) +#define MX6Q_USDHC_PAD_CTRL_47KPU_40OHM_50MHZ PAD_CTL_PIS(47K_UP, 40ohm, LOW) +#define MX6Q_USDHC_PAD_CTRL_47KPU_48OHM_50MHZ PAD_CTL_PIS(47K_UP, 48ohm, LOW) +#define MX6Q_USDHC_PAD_CTRL_47KPU_60OHM_50MHZ PAD_CTL_PIS(47K_UP, 60ohm, LOW) +#define MX6Q_USDHC_PAD_CTRL_47KPU_80OHM_50MHZ PAD_CTL_PIS(47K_UP, 80ohm, LOW) +#define MX6Q_USDHC_PAD_CTRL_47KPU_120OHM_50MHZ PAD_CTL_PIS(47K_UP, 120ohm, LOW) +#define MX6Q_USDHC_PAD_CTRL_50MHZ MX6Q_USDHC_PAD_CTRL + + +#define MX6DL_USDHC_PAD_CTRL_22KPU_34OHM_50MHZ PAD_CTL_PIS(22K_UP, 34ohm, LOW) +#define MX6DL_USDHC_PAD_CTRL_22KPU_40OHM_50MHZ PAD_CTL_PIS(22K_UP, 40ohm, LOW) +#define MX6DL_USDHC_PAD_CTRL_22KPU_48OHM_50MHZ PAD_CTL_PIS(22K_UP, 48ohm, LOW) +#define MX6DL_USDHC_PAD_CTRL_22KPU_60OHM_50MHZ PAD_CTL_PIS(22K_UP, 60ohm, LOW) +#define MX6DL_USDHC_PAD_CTRL_22KPU_80OHM_50MHZ PAD_CTL_PIS(22K_UP, 80ohm, LOW) +#define MX6DL_USDHC_PAD_CTRL_22KPU_120OHM_50MHZ PAD_CTL_PIS(22K_UP, 120ohm, LOW) +#define MX6DL_USDHC_PAD_CTRL_47KPU_34OHM_50MHZ PAD_CTL_PIS(47K_UP, 34ohm, LOW) +#define MX6DL_USDHC_PAD_CTRL_47KPU_40OHM_50MHZ PAD_CTL_PIS(47K_UP, 40ohm, LOW) +#define MX6DL_USDHC_PAD_CTRL_47KPU_48OHM_50MHZ PAD_CTL_PIS(47K_UP, 48ohm, LOW) +#define MX6DL_USDHC_PAD_CTRL_47KPU_60OHM_50MHZ PAD_CTL_PIS(47K_UP, 60ohm, LOW) +#define MX6DL_USDHC_PAD_CTRL_47KPU_80OHM_50MHZ PAD_CTL_PIS(47K_UP, 80ohm, LOW) +#define MX6DL_USDHC_PAD_CTRL_47KPU_120OHM_50MHZ PAD_CTL_PIS(47K_UP, 120ohm, LOW) +#define MX6DL_USDHC_PAD_CTRL_50MHZ MX6DL_USDHC_PAD_CTRL + +#define MX6Q_PAD_SD3_CLK__USDHC3_CLK MX6Q_PAD_SD3_CLK__USDHC3_CLK_50MHZ +#define MX6Q_PAD_SD3_CMD__USDHC3_CMD MX6Q_PAD_SD3_CMD__USDHC3_CMD_50MHZ +#define MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ +#define MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ +#define MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ +#define MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ +#define MX6Q_PAD_SD4_CLK__USDHC4_CLK MX6Q_PAD_SD4_CLK__USDHC4_CLK_50MHZ +#define MX6Q_PAD_SD4_CMD__USDHC4_CMD MX6Q_PAD_SD4_CMD__USDHC4_CMD_50MHZ +#define MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 MX6Q_PAD_SD4_DAT0__USDHC4_DAT0_50MHZ +#define MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 MX6Q_PAD_SD4_DAT1__USDHC4_DAT1_50MHZ +#define MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 MX6Q_PAD_SD4_DAT2__USDHC4_DAT2_50MHZ +#define MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 MX6Q_PAD_SD4_DAT3__USDHC4_DAT3_50MHZ +#define MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 MX6Q_PAD_SD4_DAT4__USDHC4_DAT4_50MHZ +#define MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 MX6Q_PAD_SD4_DAT5__USDHC4_DAT5_50MHZ +#define MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 MX6Q_PAD_SD4_DAT6__USDHC4_DAT6_50MHZ +#define MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 MX6Q_PAD_SD4_DAT7__USDHC4_DAT7_50MHZ + + +#define MX6DL_PAD_SD3_CLK__USDHC3_CLK MX6DL_PAD_SD3_CLK__USDHC3_CLK_50MHZ +#define MX6DL_PAD_SD3_CMD__USDHC3_CMD MX6DL_PAD_SD3_CMD__USDHC3_CMD_50MHZ +#define MX6DL_PAD_SD3_DAT0__USDHC3_DAT0 MX6DL_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ +#define MX6DL_PAD_SD3_DAT1__USDHC3_DAT1 MX6DL_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ +#define MX6DL_PAD_SD3_DAT2__USDHC3_DAT2 MX6DL_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ +#define MX6DL_PAD_SD3_DAT3__USDHC3_DAT3 MX6DL_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ +#define MX6DL_PAD_SD4_CLK__USDHC4_CLK MX6DL_PAD_SD4_CLK__USDHC4_CLK_50MHZ +#define MX6DL_PAD_SD4_CMD__USDHC4_CMD MX6DL_PAD_SD4_CMD__USDHC4_CMD_50MHZ +#define MX6DL_PAD_SD4_DAT0__USDHC4_DAT0 MX6DL_PAD_SD4_DAT0__USDHC4_DAT0_50MHZ +#define MX6DL_PAD_SD4_DAT1__USDHC4_DAT1 MX6DL_PAD_SD4_DAT1__USDHC4_DAT1_50MHZ +#define MX6DL_PAD_SD4_DAT2__USDHC4_DAT2 MX6DL_PAD_SD4_DAT2__USDHC4_DAT2_50MHZ +#define MX6DL_PAD_SD4_DAT3__USDHC4_DAT3 MX6DL_PAD_SD4_DAT3__USDHC4_DAT3_50MHZ +#define MX6DL_PAD_SD4_DAT4__USDHC4_DAT4 MX6DL_PAD_SD4_DAT4__USDHC4_DAT4_50MHZ +#define MX6DL_PAD_SD4_DAT5__USDHC4_DAT5 MX6DL_PAD_SD4_DAT5__USDHC4_DAT5_50MHZ +#define MX6DL_PAD_SD4_DAT6__USDHC4_DAT6 MX6DL_PAD_SD4_DAT6__USDHC4_DAT6_50MHZ +#define MX6DL_PAD_SD4_DAT7__USDHC4_DAT7 MX6DL_PAD_SD4_DAT7__USDHC4_DAT7_50MHZ + +#define NP(id, pin, pad_ctl) \ + NEW_PAD_CTRL(MX6PAD(SD##id##_##pin##__USDHC##id##_##pin), MX6(pad_ctl)) + +#define SD_PINS(id, pad_ctl) \ + NP(id, CLK, pad_ctl), \ + NP(id, CMD, pad_ctl), \ + NP(id, DAT0, pad_ctl), \ + NP(id, DAT1, pad_ctl), \ + NP(id, DAT2, pad_ctl), \ + NP(id, DAT3, pad_ctl) + +#define SD_PINS8(id, pad_ctl) \ + SD_PINS(id, pad_ctl), \ + NP(id, DAT4, pad_ctl), \ + NP(id, DAT5, pad_ctl), \ + NP(id, DAT6, pad_ctl), \ + NP(id, DAT7, pad_ctl) + +static iomux_v3_cfg_t MX6NAME(common_pads)[] = { + + /* CCM */ + MX6PAD(CSI0_MCLK__CCM_CLKO), /* MIPI camera mclk */ + + /* ECSPI1 */ + MX6PAD(EIM_D17__ECSPI1_MISO), + MX6PAD(EIM_D18__ECSPI1_MOSI), + MX6PAD(EIM_D16__ECSPI1_SCLK), + MX6PAD(EIM_D19__GPIO_3_19), /*SS1*/ + + /* ECSPI2 */ + MX6PAD(CSI0_DAT10__ECSPI2_MISO), + MX6PAD(CSI0_DAT9__ECSPI2_MOSI), + MX6PAD(CSI0_DAT8__ECSPI2_SCLK), + MX6PAD(CSI0_DAT11__GPIO_5_29), /*SS0*/ + + /* GPIO1 */ + MX6PAD(SD1_DAT0__GPIO_1_16), /* Main power enable */ + MX6PAD(SD1_DAT1__GPIO_1_17), /* J4 - GP */ + + /* GPIO2 */ + MX6PAD(NANDF_D1__GPIO_2_1), /* Power 5.4V enable */ + MX6PAD(NANDF_D2__GPIO_2_2), /* DC_STAT, low DC, High battery */ + MX6PAD(NANDF_D7__GPIO_2_7), /* J3 - GP */ + MX6PAD(EIM_RW__GPIO_2_26), /* J6 - GP */ + + /* GPIO4 */ + MX6PAD(EIM_DA0__GPIO_3_0), /* J4 - GP */ + MX6PAD(EIM_DA1__GPIO_3_1), /* J4 - GP */ + MX6PAD(EIM_DA2__GPIO_3_2), /* J4 - GP */ + MX6PAD(EIM_DA3__GPIO_3_3), /* J4 - GP */ + NEW_PAD_CTRL(MX6PAD(EIM_DA4__GPIO_3_4), WEAK_PULLUP), /* FXAS21000, int2 */ + NEW_PAD_CTRL(MX6PAD(EIM_DA5__GPIO_3_5), WEAK_PULLUP), /* FXAS21000, int2 */ + MX6PAD(EIM_D20__GPIO_3_20), /* J6 - GP */ + MX6PAD(EIM_D29__GPIO_3_29), /* J6 - GP */ + + /* GPIO4 */ + MX6PAD(GPIO_19__GPIO_4_5), /* J4 - GP */ + MX6PAD(KEY_COL2__GPIO_4_10), /* J4 - GP */ + MX6PAD(KEY_ROW2__GPIO_4_11), /* J4 - GP */ + + /* GPIO6 */ + NEW_PAD_CTRL(MX6PAD(NANDF_CLE__GPIO_6_7), ISL1208_IRQ_PADCFG), /* RTC ISL1208 irq*/ + MX6PAD(NANDF_CS0__GPIO_6_11), /* J4 - GP */ + + /* GPIO7 */ + NEW_PAD_CTRL(MX6PAD(SD3_DAT4__GPIO_7_1), WEAK_PULLUP), /* Main power off request, input */ + MX6PAD(GPIO_18__GPIO_7_13), /* J4 - GP */ + + /* I2C1, SGTL5000 */ + MX6PAD(EIM_D21__I2C1_SCL), /* GPIO3[21] */ + MX6PAD(EIM_D28__I2C1_SDA), /* GPIO3[28] */ + + /* I2C2 Camera, MIPI */ + MX6PAD(KEY_COL3__I2C2_SCL), /* GPIO4[12] */ + MX6PAD(KEY_ROW3__I2C2_SDA), /* GPIO4[13] */ + NEW_PAD_CTRL(MX6PAD(GPIO_9__GPIO_1_9), WEAK_PULLUP), /* I2C Touch IRQ */ + MX6PAD(NANDF_D3__GPIO_2_3), /* Touch wake */ + MX6PAD(NANDF_D4__GPIO_2_4), /* Touch reset */ + + /* I2C3 */ + MX6PAD(GPIO_5__I2C3_SCL), /* GPIO1[5] - J7 - Display card */ + MX6PAD(GPIO_16__I2C3_SDA), /* GPIO7[11] - J15 - RGB connector */ + + /* PWM1 */ + MX6PAD(SD1_DAT3__PWM1_PWMO), /* GPIO1[21] */ + + /* PWM2 */ + MX6PAD(SD1_DAT2__PWM2_PWMO), /* GPIO1[19] */ + + /* UART1 */ + MX6PAD(SD3_DAT7__UART1_TXD), + MX6PAD(SD3_DAT6__UART1_RXD), + + /* UART2 for debug */ + MX6PAD(EIM_D26__UART2_TXD), + MX6PAD(EIM_D27__UART2_RXD), + + /* UART3 for wl1271 */ + MX6PAD(EIM_D24__UART3_TXD), + MX6PAD(EIM_D25__UART3_RXD), + MX6PAD(EIM_D23__UART3_CTS), + MX6PAD(EIM_D31__UART3_RTS), + + /* USB H1 */ + MX6PAD(EIM_D30__USBOH3_USBH1_OC), + + /* USBOTG ID pin */ + MX6PAD(GPIO_1__USBOTG_ID), + MX6PAD(KEY_COL4__USBOH3_USBOTG_OC), + NEW_PAD_CTRL(MX6PAD(EIM_D22__GPIO_3_22), WEAK_PULLUP), + + /* USDHC2 (WiFi) */ + SD_PINS(2, USDHC_PAD_CTRL_22KPU_40OHM_50MHZ), + MX6PAD(SD1_CLK__OSC32K_32K_OUT), /* wl1271 clock */ + NEW_PAD_CTRL(MX6PAD(NANDF_CS1__GPIO_6_14), N6_IRQ_PADCFG), /* wl1271 wl_irq */ + NEW_PAD_CTRL(MX6PAD(NANDF_CS2__GPIO_6_15), N6_EN_PADCFG), /* wl1271 wl_en */ + NEW_PAD_CTRL(MX6PAD(NANDF_CS3__GPIO_6_16), N6_EN_PADCFG), /* wl1271 bt_en */ + + /* USDHC3 */ + SD_PINS(3, USDHC_PAD_CTRL_50MHZ), + MX6PAD(SD3_DAT5__GPIO_7_0), /* SD3_CD */ + + /* USDHC4 (eMMC) */ + SD_PINS8(4, USDHC_PAD_CTRL_50MHZ), + MX6PAD(EIM_CS0__GPIO_2_23), /* eMMC reset */ + 0 +}; + +static iomux_v3_cfg_t MX6NAME(lcd_pads_enable)[] = { + MX6PAD(DI0_DISP_CLK__IPU1_DI0_DISP_CLK), + MX6PAD(DI0_PIN15__IPU1_DI0_PIN15), /* DE */ + MX6PAD(DI0_PIN2__IPU1_DI0_PIN2), /* HSync */ + MX6PAD(DI0_PIN3__IPU1_DI0_PIN3), /* VSync */ + MX6PAD(DISP0_DAT0__IPU1_DISP0_DAT_0), + MX6PAD(DISP0_DAT1__IPU1_DISP0_DAT_1), + MX6PAD(DISP0_DAT2__IPU1_DISP0_DAT_2), + MX6PAD(DISP0_DAT3__IPU1_DISP0_DAT_3), + MX6PAD(DISP0_DAT4__IPU1_DISP0_DAT_4), + MX6PAD(DISP0_DAT5__IPU1_DISP0_DAT_5), + MX6PAD(DISP0_DAT6__IPU1_DISP0_DAT_6), + MX6PAD(DISP0_DAT7__IPU1_DISP0_DAT_7), + MX6PAD(DISP0_DAT8__IPU1_DISP0_DAT_8), + MX6PAD(DISP0_DAT9__IPU1_DISP0_DAT_9), + MX6PAD(DISP0_DAT10__IPU1_DISP0_DAT_10), + MX6PAD(DISP0_DAT11__IPU1_DISP0_DAT_11), + MX6PAD(DISP0_DAT12__IPU1_DISP0_DAT_12), + MX6PAD(DISP0_DAT13__IPU1_DISP0_DAT_13), + MX6PAD(DISP0_DAT14__IPU1_DISP0_DAT_14), + MX6PAD(DISP0_DAT15__IPU1_DISP0_DAT_15), + MX6PAD(DISP0_DAT16__IPU1_DISP0_DAT_16), + MX6PAD(DISP0_DAT17__IPU1_DISP0_DAT_17), + MX6PAD(DISP0_DAT18__IPU1_DISP0_DAT_18), + MX6PAD(DISP0_DAT19__IPU1_DISP0_DAT_19), + MX6PAD(DISP0_DAT20__IPU1_DISP0_DAT_20), + MX6PAD(DISP0_DAT21__IPU1_DISP0_DAT_21), + MX6PAD(DISP0_DAT22__IPU1_DISP0_DAT_22), + MX6PAD(DISP0_DAT23__IPU1_DISP0_DAT_23), + 0 +}; + +static iomux_v3_cfg_t MX6NAME(lcd_pads_disable)[] = { + MX6PAD(DI0_DISP_CLK__GPIO_4_16), + MX6PAD(DI0_PIN15__GPIO_4_17), /* DE */ + MX6PAD(DI0_PIN2__GPIO_4_18), /* HSync */ + MX6PAD(DI0_PIN3__GPIO_4_19), /* VSync */ + MX6PAD(DISP0_DAT0__GPIO_4_21), + MX6PAD(DISP0_DAT1__GPIO_4_22), + MX6PAD(DISP0_DAT2__GPIO_4_23), + MX6PAD(DISP0_DAT3__GPIO_4_24), + MX6PAD(DISP0_DAT4__GPIO_4_25), + MX6PAD(DISP0_DAT5__GPIO_4_26), + MX6PAD(DISP0_DAT6__GPIO_4_27), + MX6PAD(DISP0_DAT7__GPIO_4_28), + MX6PAD(DISP0_DAT8__GPIO_4_29), + MX6PAD(DISP0_DAT9__GPIO_4_30), + MX6PAD(DISP0_DAT10__GPIO_4_31), + MX6PAD(DISP0_DAT11__GPIO_5_5), + MX6PAD(DISP0_DAT12__GPIO_5_6), + MX6PAD(DISP0_DAT13__GPIO_5_7), + MX6PAD(DISP0_DAT14__GPIO_5_8), + MX6PAD(DISP0_DAT15__GPIO_5_9), + MX6PAD(DISP0_DAT16__GPIO_5_10), + MX6PAD(DISP0_DAT17__GPIO_5_11), + MX6PAD(DISP0_DAT18__GPIO_5_12), + MX6PAD(DISP0_DAT19__GPIO_5_13), + MX6PAD(DISP0_DAT20__GPIO_5_14), + MX6PAD(DISP0_DAT21__GPIO_5_15), + MX6PAD(DISP0_DAT22__GPIO_5_16), + MX6PAD(DISP0_DAT23__GPIO_5_17), + 0 +}; + +static iomux_v3_cfg_t MX6NAME(mipi_pads)[] = { + MX6PAD(CSI0_DATA_EN__GPIO_5_20), /* Mipi Camera Reset */ + MX6PAD(CSI0_VSYNC__GPIO_5_21), /* Mipi Powerdown */ + 0 +}; + +static iomux_v3_cfg_t MX6NAME(hdmi_ddc_pads)[] = { + MX6PAD(KEY_COL3__HDMI_TX_DDC_SCL), /* HDMI DDC SCL */ + MX6PAD(KEY_ROW3__HDMI_TX_DDC_SDA), /* HDMI DDC SDA */ + 0 +}; + +static iomux_v3_cfg_t MX6NAME(i2c2_pads)[] = { + MX6PAD(KEY_COL3__I2C2_SCL), /* I2C2 SCL */ + MX6PAD(KEY_ROW3__I2C2_SDA), /* I2C2 SDA */ + 0 +}; + +#define MX6_USDHC_PAD_SETTING(id, speed, pad_ctl) \ + MX6NAME(sd##id##_##speed##mhz)[] = { SD_PINS(id, pad_ctl), 0 } + +#define MX6_USDHC_PAD_SETTING8(id, speed, pad_ctl) \ + MX6NAME(sd##id##_##speed##mhz)[] = { SD_PINS8(id, pad_ctl), 0 } + +static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(2, 50, USDHC_PAD_CTRL_22KPU_40OHM_50MHZ); +static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(2, 100, USDHC_PAD_CTRL_100MHZ); +static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(2, 200, USDHC_PAD_CTRL_200MHZ); +static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(3, 50, USDHC_PAD_CTRL_50MHZ); +static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(3, 100, USDHC_PAD_CTRL_100MHZ); +static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING(3, 200, USDHC_PAD_CTRL_200MHZ); +static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING8(4, 50, USDHC_PAD_CTRL_50MHZ); +static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING8(4, 100, USDHC_PAD_CTRL_100MHZ); +static iomux_v3_cfg_t MX6_USDHC_PAD_SETTING8(4, 200, USDHC_PAD_CTRL_200MHZ); + +#define _50MHZ 0 +#define _100MHZ 1 +#define _200MHZ 2 +#define SD_SPEED_CNT 3 +static iomux_v3_cfg_t * MX6NAME(sd_pads)[] = +{ + MX6NAME(sd2_50mhz), + MX6NAME(sd2_100mhz), + MX6NAME(sd2_200mhz), + MX6NAME(sd3_50mhz), + MX6NAME(sd3_100mhz), + MX6NAME(sd3_200mhz), + MX6NAME(sd4_50mhz), + MX6NAME(sd4_100mhz), + MX6NAME(sd4_200mhz), +}; diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types index 292f2e0bba09..e017ff5423e7 100644 --- a/arch/arm/tools/mach-types +++ b/arch/arm/tools/mach-types @@ -1121,6 +1121,7 @@ mx6_oc MACH_MX6_OC MX6_OC 3770 mx6_nit6xlite MACH_MX6_NIT6XLITE MX6_NIT6XLITE 3771 mx6_h MACH_MX6_H MX6_H 3772 mx6_utc MACH_MX6_UTC MX6_UTC 3773 +mx6_r MACH_MX6_R MX6_R 3774 mx6q_sabresd MACH_MX6Q_SABRESD MX6Q_SABRESD 3980 mx6q_arm2 MACH_MX6Q_ARM2 MX6Q_ARM2 3837 mx6sl_arm2 MACH_MX6SL_ARM2 MX6SL_ARM2 4091 diff --git a/drivers/rtc/rtc-isl1208.c b/drivers/rtc/rtc-isl1208.c index 4b2788ce7f5c..7137b55b9367 100644 --- a/drivers/rtc/rtc-isl1208.c +++ b/drivers/rtc/rtc-isl1208.c @@ -118,7 +118,7 @@ isl1208_i2c_set_regs(struct i2c_client *client, u8 reg, u8 const buf[], return ret; } -/* simple check to see wether we have a isl1208 */ +/* simple check to see whether we have a isl1208 */ static int isl1208_i2c_validate_client(struct i2c_client *client) { @@ -659,7 +659,7 @@ isl1208_probe(struct i2c_client *client, const struct i2c_device_id *id) if (client->irq > 0) { rc = request_threaded_irq(client->irq, NULL, isl1208_rtc_interrupt, - IRQF_SHARED | IRQF_TRIGGER_FALLING, + IRQF_SHARED | IRQF_ONESHOT | IRQF_TRIGGER_FALLING, isl1208_driver.driver.name, client); if (!rc) { device_init_wakeup(&client->dev, 1); diff --git a/drivers/video/mxc/mxc_lcdif.c b/drivers/video/mxc/mxc_lcdif.c index ddc00e4559a0..2b484588d962 100644 --- a/drivers/video/mxc/mxc_lcdif.c +++ b/drivers/video/mxc/mxc_lcdif.c @@ -57,6 +57,15 @@ static struct fb_videomode lcdif_modedb[] = { .sync = FB_SYNC_CLK_LAT_FALL, .vmode = FB_VMODE_NONINTERLACED, .flag = 0,}, + { + /* 480x800 @ 57 Hz , pixel clk @ 27MHz */ + "LB043", 57, 480, 800, 25000, + .left_margin = 40, .right_margin = 60, + .upper_margin = 10, .lower_margin = 10, + .hsync_len = 20, .vsync_len = 10, + .sync = FB_SYNC_CLK_LAT_FALL, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0,}, }; static int lcdif_modedb_sz = ARRAY_SIZE(lcdif_modedb); |