diff options
| author | Thomas Abraham <thomas.abraham@linaro.org> | 2012-07-14 10:53:08 +0900 |
|---|---|---|
| committer | Kukjin Kim <kgene.kim@samsung.com> | 2012-07-14 10:57:02 +0900 |
| commit | 46fda15c0c21493a9305db0a05e08f072d6409e4 (patch) | |
| tree | 4dba60a35f41a10796d0931f34a5c7922c1c290f | |
| parent | 4922972ecaca1b2eeb0f7643f97006d2f713d42b (diff) | |
ARM: EXYNOS: Fix the incorrect hierarchy of spi controller bus clock
The sclk_spi clock is derived currently from the first level divider
(MMCx_RATIO) which is incorrect. The output of the first level clock
is divided by a second level divider (MMCx_PRE_RATIO), the output of
which is used as the spi bus clock (sclk_spi). Fix the clock hierarchy
issues for the sclk_spi clock.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Jaswinder Singh <jaswinder.singh@linaro.org>
[kgene.kim@samsung.com: changed the name of clk for consensus]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| -rw-r--r-- | arch/arm/mach-exynos/clock-exynos4.c | 49 |
1 files changed, 39 insertions, 10 deletions
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c index 10a46a9f0ea7..26fe9de35ecb 100644 --- a/arch/arm/mach-exynos/clock-exynos4.c +++ b/arch/arm/mach-exynos/clock-exynos4.c @@ -1242,40 +1242,67 @@ static struct clksrc_clk exynos4_clk_sclk_mmc3 = { .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 }, }; +static struct clksrc_clk exynos4_clk_mdout_spi0 = { + .clk = { + .name = "mdout_spi", + .devname = "exynos4210-spi.0", + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 }, +}; + +static struct clksrc_clk exynos4_clk_mdout_spi1 = { + .clk = { + .name = "mdout_spi", + .devname = "exynos4210-spi.1", + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 }, +}; + +static struct clksrc_clk exynos4_clk_mdout_spi2 = { + .clk = { + .name = "mdout_spi", + .devname = "exynos4210-spi.2", + }, + .sources = &exynos4_clkset_group, + .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 }, +}; + static struct clksrc_clk exynos4_clk_sclk_spi0 = { .clk = { .name = "sclk_spi", .devname = "exynos4210-spi.0", + .parent = &exynos4_clk_mdout_spi0.clk, .enable = exynos4_clksrc_mask_peril1_ctrl, .ctrlbit = (1 << 16), }, - .sources = &exynos4_clkset_group, - .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 }, - .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 8, .size = 8 }, }; static struct clksrc_clk exynos4_clk_sclk_spi1 = { .clk = { .name = "sclk_spi", .devname = "exynos4210-spi.1", + .parent = &exynos4_clk_mdout_spi1.clk, .enable = exynos4_clksrc_mask_peril1_ctrl, .ctrlbit = (1 << 20), }, - .sources = &exynos4_clkset_group, - .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 }, - .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 24, .size = 8 }, }; static struct clksrc_clk exynos4_clk_sclk_spi2 = { .clk = { .name = "sclk_spi", .devname = "exynos4210-spi.2", + .parent = &exynos4_clk_mdout_spi2.clk, .enable = exynos4_clksrc_mask_peril1_ctrl, .ctrlbit = (1 << 24), }, - .sources = &exynos4_clkset_group, - .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 }, - .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 }, + .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 8, .size = 8 }, }; /* Clock initialization code */ @@ -1331,7 +1358,9 @@ static struct clksrc_clk *exynos4_clksrc_cdev[] = { &exynos4_clk_sclk_spi0, &exynos4_clk_sclk_spi1, &exynos4_clk_sclk_spi2, - + &exynos4_clk_mdout_spi0, + &exynos4_clk_mdout_spi1, + &exynos4_clk_mdout_spi2, }; static struct clk_lookup exynos4_clk_lookup[] = { |