fsl-imx8qxp-colibri-eval-v3.dts: rework into a dtsi and a display specific dts

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>

3 files changed, 135 insertions, 986 deletions

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dts
index 4566d8bc71d8..e5b4e030b100 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dts
@@ -16,22 +16,11 @@
 //#define IS_A0_SILICON
 
 #include "dt-bindings/pwm/pwm.h"
-#include "fsl-imx8qxp.dtsi"
-
+#include "fsl-imx8qxp-colibri-eval-v3.dtsi"
 / {
 	model = "Toradex Colibri iMX8QXP";
 	compatible = "toradex,imx8qxp-colibri", "fsl,imx8qxp";
 
-	aliases {
-		rtc0 = &rtc_i2c;
-		rtc1 = &rtc;
-	};
-
-	chosen {
-		bootargs = "console=ttyLP3,115200 earlycon=lpuart32,0x5a090000,115200";
-		stdout-path = &lpuart3;
-	};
-
 	backlight: backlight {
 		compatible = "pwm-backlight";
 		pinctrl-names = "default";
@@ -48,14 +37,6 @@
 		status = "disabled";
 	};
 
-	extcon_usbc_det: usbc_det {
-		compatible = "linux,extcon-usb-gpio";
-		debounce = <25>;
-		id-gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_usbc_det &pinctrl_ext_io0>;
-	};
-
 	panel {
 		compatible = "edt,et070080dh6";
 		backlight = <&backlight>;
@@ -89,437 +70,7 @@
 	};
 #endif
 
-	regulators {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		reg_module_3v3: regulator-module-3v3 {
-			compatible = "regulator-fixed";
-			regulator-name = "+V3.3";
-			regulator-min-microvolt = <3300000>;
-			regulator-max-microvolt = <3300000>;
-		};
-
-		reg_module_3v3_avdd: regulator-module-3v3-avdd {
-			compatible = "regulator-fixed";
-			regulator-name = "+V3.3_AVDD_AUDIO";
-			regulator-min-microvolt = <3300000>;
-			regulator-max-microvolt = <3300000>;
-		};
-
-		reg_vref_1v8: regulator-vref-1v8 {
-			compatible = "regulator-fixed";
-			regulator-name = "vref-1v8";
-			regulator-min-microvolt = <1800000>;
-			regulator-max-microvolt = <1800000>;
-		};
-
-		reg_usbh_vbus: regulator-usbh-vbus {
-			compatible = "regulator-fixed";
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_usbh1_reg>;
-			regulator-name = "usbh_vbus";
-			regulator-min-microvolt = <5000000>;
-			regulator-max-microvolt = <5000000>;
-			gpio = <&gpio4 3 GPIO_ACTIVE_LOW>;
-			regulator-always-on;
-		};
-	};
-
-	sound {
-		compatible = "simple-audio-card";
-		simple-audio-card,name = "imx8qxp-sgtl5000";
-		simple-audio-card,format = "i2s";
-		simple-audio-card,bitclock-master = <&dailink_master>;
-		simple-audio-card,frame-master = <&dailink_master>;
-		/*simple-audio-card,mclk-fs = <1>;*/
-		simple-audio-card,cpu {
-			sound-dai = <&sai0>;
-		};
-
-		dailink_master: simple-audio-card,codec {
-			sound-dai = <&sgtl5000>;
-			clocks = <&clk IMX8QXP_AUD_MCLKOUT0>;
-		};
-	};
-};
-
-&iomuxc {
-	pinctrl-names = "default";
-	imx8qxp-colibri {
-
-		pinctrl_ad7879_int: ad7879-int { /* TOUCH Interrupt */
-			fsl,pins = <
-				SC_P_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05	0x00000021
-			>;
-		};
-
-		pinctrl_adc0: adc0grp {
-			fsl,pins = <
-				SC_P_ADC_IN0_ADMA_ADC_IN0		0x60
-				SC_P_ADC_IN1_ADMA_ADC_IN1		0x60
-				SC_P_ADC_IN4_ADMA_ADC_IN4		0x60
-				SC_P_ADC_IN5_ADMA_ADC_IN5		0x60
-			>;
-		};
-
-		pinctrl_lpuart0: lpuart0grp {
-			fsl,pins = <
-				SC_P_UART0_RX_ADMA_UART0_RX	0x06000020
-				SC_P_UART0_TX_ADMA_UART0_TX	0x06000020
-				SC_P_FLEXCAN0_RX_ADMA_UART0_RTS_B	0x06000020
-				SC_P_FLEXCAN0_TX_ADMA_UART0_CTS_B	0x06000020
-			>;
-		};
-
-		pinctrl_lpuart2: lpuart2grp {
-			fsl,pins = <
-				SC_P_UART2_RX_ADMA_UART2_RX	0x06000020
-				SC_P_UART2_TX_ADMA_UART2_TX	0x06000020
-			>;
-		};
-
-		pinctrl_lpuart3: lpuart3grp {
-			fsl,pins = <
-				SC_P_FLEXCAN2_RX_ADMA_UART3_RX	0x06000020
-				SC_P_FLEXCAN2_TX_ADMA_UART3_TX	0x06000020
-			>;
-		};
-
-		pinctrl_fec1: fec1grp {
-			fsl,pins = <
-				SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000020
-				SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
-				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000061
-				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT	0x06000061
-				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x00000061
-				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x00000061
-				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x00000061
-				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x00000061
-				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x00000061
-				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER	0x00000061
-			>;
-		};
-
-		pinctrl_fec1_sleep: fec1-sleep-grp {
-			fsl,pins = <
-				SC_P_ENET0_MDC_LSIO_GPIO5_IO11			0x06000041
-				SC_P_ENET0_MDIO_LSIO_GPIO5_IO10			0x06000041
-				SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30		0x00000041
-				SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29		0x00000041
-				SC_P_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31		0x00000041
-				SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00		0x00000041
-				SC_P_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04		0x00000041
-				SC_P_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05		0x00000041
-				SC_P_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06		0x00000041
-				SC_P_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07		0x00000041
-			>;
-		};
-
-		pinctrl_gpio_bl_on: gpio-bl-on {
-			fsl,pins = <
-				SC_P_QSPI0A_DATA3_LSIO_GPIO3_IO12	0x00000040
-			>;
-		};
-
-		/* On Module I2C */
-		pinctrl_i2c0: i2c0grp {
-			fsl,pins = <
-				SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL	0x06000021
-				SC_P_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA	0x06000021
-			>;
-		};
-
-		/* Off Module I2C */
-		pinctrl_i2c1: i2c1grp {
-			fsl,pins = <
-				SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL	0x06000021
-				SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA	0x06000021
-			>;
-		};
-
-		pinctrl_flexcan1: flexcan0grp {
-			fsl,pins = <
-				SC_P_FLEXCAN0_TX_ADMA_FLEXCAN0_TX		0x21
-				SC_P_FLEXCAN0_RX_ADMA_FLEXCAN0_RX		0x21
-			>;
-		};
-
-		pinctrl_flexcan2: flexcan1grp {
-			fsl,pins = <
-				SC_P_FLEXCAN1_TX_ADMA_FLEXCAN1_TX		0x21
-				SC_P_FLEXCAN1_RX_ADMA_FLEXCAN1_RX		0x21
-			>;
-		};
-
-		pinctrl_pcieb: pciebgrp {
-			fsl,pins = <
-				SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x04000061
-				SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02	0x04000061
-				SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00	0x00000060
-			>;
-		};
-
-		pinctrl_pwm_a: pwma {
-		/* both pins are connected together, reserve the unused CSI_D05 */
-			fsl,pins = <
-				SC_P_CSI_D05_CI_PI_D07			0x00000061
-				SC_P_SPI0_CS1_ADMA_LCD_PWM0_OUT		0x00000060
-			>;
-		};
-
-		pinctrl_pwm_b: pwmb {
-			fsl,pins = <
-				SC_P_UART1_TX_LSIO_PWM0_OUT		0x00000060
-			>;
-		};
-
-		pinctrl_pwm_c: pwmc {
-			fsl,pins = <
-				SC_P_UART1_RX_LSIO_PWM1_OUT		0x00000060
-			>;
-		};
-
-		pinctrl_pwm_d: pwmd {
-		/* both pins are connected together, reserve the unused CSI_D04 */
-			fsl,pins = <
-				SC_P_CSI_D04_CI_PI_D06			0x00000061
-				SC_P_UART1_RTS_B_LSIO_PWM2_OUT		0x00000060
-			>;
-		};
-
-		pinctrl_sai0: sai0grp {
-			fsl,pins = <
-				SC_P_SPI0_SDI_ADMA_SAI0_TXD		0x06000040
-				SC_P_SPI0_CS0_ADMA_SAI0_RXD		0x06000040
-				SC_P_SPI0_SCK_ADMA_SAI0_TXC		0x06000040
-				SC_P_SPI0_SDO_ADMA_SAI0_TXFS		0x06000040
-			>;
-		};
-
-		pinctrl_sgtl5000: sgtl5000 {
-			fsl,pins = <
-				/* MIC GND EN */
-				SC_P_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 0x00000041
-			>;
-		};
-
-		pinctrl_sgtl5000_usb_clk: sgtl5000-usb-clk {
-			fsl,pins = <
-				SC_P_ADC_IN3_ADMA_ACM_MCLK_OUT0		0x00000021
-			>;
-		};
-
-		/*INT*/
-		pinctrl_usb3503a: usb3503a-grp {
-			fsl,pins = <
-				SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x00000061
-			>;
-		};
-
-		pinctrl_usbc_det: usbc-det {
-			fsl,pins = <
-				SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09	0x06000040
-			>;
-		};
-
-		pinctrl_ext_io0: ext-io0 {
-			fsl,pins = <
-				SC_P_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08	0x06000040
-			>;
-		};
-
-		pinctrl_lcdif: lcdif-pins {
-			fsl,pins = <
-				SC_P_MCLK_OUT0_ADMA_LCDIF_CLK		0x00000060
-				SC_P_SPI3_CS0_ADMA_LCDIF_HSYNC		0x00000060
-				SC_P_MCLK_IN0_ADMA_LCDIF_VSYNC		0x00000060
-				SC_P_MCLK_IN1_ADMA_LCDIF_EN		0x00000060
-				  SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19	0x00000060
-
-				SC_P_ESAI0_FSR_ADMA_LCDIF_D00		0x00000060
-				  SC_P_USDHC1_WP_LSIO_GPIO4_IO21	0x00000060
-				SC_P_ESAI0_FST_ADMA_LCDIF_D01		0x00000060
-				SC_P_ESAI0_SCKR_ADMA_LCDIF_D02		0x00000060
-				SC_P_ESAI0_SCKT_ADMA_LCDIF_D03		0x00000060
-				SC_P_ESAI0_TX0_ADMA_LCDIF_D04		0x00000060
-				SC_P_ESAI0_TX1_ADMA_LCDIF_D05		0x00000060
-				SC_P_ESAI0_TX2_RX3_ADMA_LCDIF_D06	0x00000060
-				SC_P_ESAI0_TX3_RX2_ADMA_LCDIF_D07	0x00000060
-				SC_P_ESAI0_TX4_RX1_ADMA_LCDIF_D08	0x00000060
-				SC_P_ESAI0_TX5_RX0_ADMA_LCDIF_D09	0x00000060
-				SC_P_SPDIF0_RX_ADMA_LCDIF_D10		0x00000060
-				SC_P_SPDIF0_TX_ADMA_LCDIF_D11		0x00000060
-				SC_P_SPDIF0_EXT_CLK_ADMA_LCDIF_D12	0x00000060
-				SC_P_SPI3_SCK_ADMA_LCDIF_D13		0x00000060
-				SC_P_SPI3_SDO_ADMA_LCDIF_D14		0x00000060
-				SC_P_SPI3_SDI_ADMA_LCDIF_D15		0x00000060
-				SC_P_SPI3_CS1_ADMA_LCDIF_D16		0x00000060
-				  SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01	0x00000060
-				SC_P_UART1_CTS_B_ADMA_LCDIF_D17		0x00000060
-			>;
-		};
-
-		pinctrl_usbh1_reg: usbh1-reg {
-			fsl,pins = <
-				SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03	0x06000040
-			>;
-		};
-
-		pinctrl_usdhc1: usdhc1grp {
-			fsl,pins = <
-				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
-				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
-				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
-				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
-				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
-				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
-				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
-				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
-				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
-				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
-				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
-				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
-			>;
-		};
-
-		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
-			fsl,pins = <
-				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
-				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
-				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
-				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
-				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
-				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
-				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
-				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
-				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
-				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
-				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
-				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
-			>;
-		};
-
-		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
-			fsl,pins = <
-				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
-				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
-				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
-				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
-				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
-				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
-				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
-				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
-				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
-				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
-				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
-				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
-			>;
-		};
-
-		pinctrl_usdhc2_gpio: usdhc2gpiogrp {
-			fsl,pins = <
-				SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09	0x06000021
-			>;
-		};
-
-		pinctrl_usdhc2: usdhc2grp {
-			fsl,pins = <
-				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041
-				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021
-				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000021
-				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000021
-				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000021
-				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000021
-				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
-			>;
-		};
-
-		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
-			fsl,pins = <
-				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041
-				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021
-				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000021
-				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000021
-				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000021
-				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000021
-				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
-			>;
-		};
-
-		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
-			fsl,pins = <
-				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041
-				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021
-				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000021
-				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000021
-				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000021
-				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000021
-				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
-			>;
-		};
-#if 0
-		pinctrl_flexspi0: flexspi0grp {
-			fsl,pins = <
-				SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0	0x0600004c
-				SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1	0x0600004c
-				SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2	0x0600004c
-				SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3	0x0600004c
-				SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS		0x0600004c
-				SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B	0x0600004c
-				SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B	0x0600004c
-				SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK	0x0600004c
-				SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK	0x0600004c
-				SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0	0x0600004c
-				SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1	0x0600004c
-				SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2	0x0600004c
-				SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3	0x0600004c
-				SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS		0x0600004c
-				SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B	0x0600004c
-				SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B	0x0600004c
-			>;
-		};
-#endif
-		pinctrl_i2c0_mipi_lvds0: mipi_lvds0_i2c0_grp {
-			fsl,pins = <
-				SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020
-				SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020
-			>;
-		};
-
-		pinctrl_i2c0_mipi_lvds1: mipi_lvds1_i2c0_grp {
-			fsl,pins = <
-				SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020
-				SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020
-			>;
-		};
-
-		pinctrl_lpspi2: lpspi2 {
-			fsl,pins = <
-				SC_P_SPI2_CS0_LSIO_GPIO1_IO00	0x00000021
-				SC_P_SPI2_SDO_ADMA_SPI2_SDO	0x06000040
-				SC_P_SPI2_SDI_ADMA_SPI2_SDI	0x06000040
-				SC_P_SPI2_SCK_ADMA_SPI2_SCK	0x06000040
-			>;
-		};
-
-		pinctrl_wifi: wifigrp {
-			fsl,pins = <
-				SC_P_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x00000020
-			>;
-		};
-	};
-};
-
-#ifndef IS_A0_SILICON
-&adc0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_adc0>;
-	vref-supply = <&reg_vref_1v8>;
-	status = "okay";
 };
-#endif
 
 &adma_lcdif {
 	pinctrl-names = "default";
@@ -533,269 +84,6 @@
 	};
 };
 
-/* CAN on UART_B RTS/CTS */
-&flexcan1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_flexcan1>;
-	xceiver-supply = <&reg_module_3v3>;
-	status = "disabled";
-};
-
-&flexcan2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_flexcan2>;
-	xceiver-supply = <&reg_module_3v3>;
-	status = "okay";
-};
-
-&lpuart0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_lpuart0>;
-	status = "okay";
-};
-
-&lpuart2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_lpuart2>;
-	status = "okay";
-};
-
-&pd_dma_lpuart3 {
-	debug_console;
-};
-
-&lpuart3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_lpuart3>;
-	status = "okay";
-};
-
-&gpio0 {
-	status = "okay";
-};
-
-&gpio1 {
-	status = "okay";
-};
-
-&gpio3 {
-	status = "okay";
-};
-
-&gpio4 {
-	status = "okay";
-};
-
-&pixel_combiner {
-	status = "okay";
-};
-
-&prg1 {
-	status = "okay";
-};
-
-&prg2 {
-	status = "okay";
-};
-
-&prg3 {
-	status = "okay";
-};
-
-&prg4 {
-	status = "okay";
-};
-
-&prg5 {
-	status = "okay";
-};
-
-&prg6 {
-	status = "okay";
-};
-
-&prg7 {
-	status = "okay";
-};
-
-&prg8 {
-	status = "okay";
-};
-
-&prg9 {
-	status = "okay";
-};
-
-/* Display Prefetch Resolve, (Tiling) */
-&dpr1_channel1 {
-	status = "okay";
-};
-
-&dpr1_channel2 {
-	status = "okay";
-};
-
-&dpr1_channel3 {
-	status = "okay";
-};
-
-&dpr2_channel1 {
-	status = "okay";
-};
-
-&dpr2_channel2 {
-	status = "okay";
-};
-
-&dpr2_channel3 {
-	status = "okay";
-};
-
-&dpu1 {
-	status = "okay";
-};
-
-&gpu_3d0 {
-	status = "okay";
-};
-
-&imx8_gpu_ss {
-	status = "okay";
-};
-
-&fec1 {
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&pinctrl_fec1>;
-	pinctrl-1 = <&pinctrl_fec1_sleep>;
-	clocks = <&clk IMX8QXP_ENET0_IPG_CLK>,
-		 <&clk IMX8QXP_ENET0_AHB_CLK>,
-		 <&clk IMX8QXP_ENET0_REF_50MHZ_CLK>,
-		 <&clk IMX8QXP_ENET0_PTP_CLK>,
-		 <&clk IMX8QXP_ENET0_TX_CLK>;
-	phy-mode = "rmii";
-	phy-handle = <&ethphy0>;
-	fsl,magic-packet;
-	status = "okay";
-
-	mdio {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		ethphy0: ethernet-phy@2 {
-			compatible = "ethernet-phy-ieee802.3-c22";
-			max-speed = <100>;
-			reg = <2>;
-		};
-	};
-};
-#if 0
-&flexspi0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_flexspi0>;
-	status = "okay";
-
-	flash0: mt35xu512aba@0 {
-		reg = <0>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "spi-flash";
-		spi-max-frequency = <29000000>;
-		spi-nor,ddr-quad-read-dummy = <8>;
-	};
-};
-#endif
-
-&i2c0 {
-	#address-cells = <1>;
-	#size-cells = <0>;
-	clock-frequency = <100000>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_i2c0>, <&pinctrl_sgtl5000_usb_clk>;
-	status = "okay";
-
-	/* IMX8QXP_AUD_MCLKOUT0 is used by both the usb3803 and sgtl5000
-	   So do the pinmuxing and setup for both here */
-	assigned-clocks = <&clk IMX8QXP_AUD_PLL0_DIV>,
-			  <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>,
-			  <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>,
-			  <&clk IMX8QXP_AUD_MCLKOUT0>;
-	assigned-clock-rates = <786432000>, <49152000>, <12000000>, <12000000>;
-
-	/* USB3503A */
-	usb3803@08 {
-		compatible = "smsc,usb3803";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_usb3503a>;
-		reg = <0x08>;
-		clocks = <&clk IMX8QXP_AUD_MCLKOUT0>;
-		clock-names = "refclk";
-		power-domains = <&pd_mclk_out0>;
-		bypass-gpios = <&gpio_expander_43 5 GPIO_ACTIVE_LOW>;
-		connect-gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
-		intn-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
-		reset-gpios = <&gpio_expander_43 4 GPIO_ACTIVE_LOW>;
-		disabled-ports = <2>;
-		initial-mode = <1>;
-		non-removable-devices = <1>;
-	};
-
-	/* SGTL5000 */
-	sgtl5000: codec@a {
-		compatible = "fsl,sgtl5000";
-		#sound-dai-cells = <0>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_sgtl5000>;
-		reg = <0x0a>;
-		clocks = <&clk IMX8QXP_AUD_MCLKOUT0>;
-		power-domains = <&pd_mclk_out0>;
-		VDDA-supply = <&reg_module_3v3_avdd>;
-		VDDIO-supply = <&reg_module_3v3>;
-		VDDD-supply = <&reg_vref_1v8>;
-	};
-
-	/* GPIO expander */
-	gpio_expander_43: gpio-expander@43 {
-		compatible = "fcs,fxl6408";
-		gpio-controller;
-		#gpio-cells = <2>;
-		reg = <0x43>;
-		inital_io_dir = <0xff>;
-		inital_output = <0x05>;
-	};
-
-	/* Touch controller */
-	ad7879@2c {
-		compatible = "adi,ad7879-1";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_ad7879_int>;
-		reg = <0x2c>;
-		interrupt-parent = <&gpio3>;
-		interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
-		touchscreen-max-pressure = <4096>;
-		adi,resistance-plate-x = <120>;
-		adi,first-conversion-delay = /bits/ 8 <3>;
-		adi,acquisition-time = /bits/ 8 <1>;
-		adi,median-filter-size = /bits/ 8 <2>;
-		adi,averaging = /bits/ 8 <1>;
-		adi,conversion-interval = /bits/ 8 <255>;
-	};
-};
-
-&i2c1 {
-	#address-cells = <1>;
-	#size-cells = <0>;
-	clock-frequency = <100000>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_i2c1>;
-	status = "okay";
-
-	/* M41T0M6 real time clock on carrier board */
-	rtc_i2c: rtc@68 {
-		compatible = "st,m41t0";
-		reg = <0x68>;
-	};
-};
-
 /* DSI/LVDS port 0 */
 &i2c0_mipi_lvds0 {
 	#address-cells = <1>;
@@ -870,161 +158,3 @@
 	status = "okay";
 };
 
-&lpspi2 {
-	#address-cells = <1>;
-	#size-cells = <0>;
-	fsl,spi-num-chipselects = <1>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_lpspi2>;
-	cs-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
-	status = "okay";
-
-	spidev0: spidev@0 {
-		compatible = "spidev";
-		reg = <0>;
-		spi-max-frequency = <10000000>;
-        };
-};
-
-&pcieb{
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_pcieb &pinctrl_wifi>;
-
-	ext_osc = <1>;
-
-	clkreq-gpio = <&gpio_expander_43 3 GPIO_ACTIVE_HIGH>;
-	disable-gpio = <&gpio_expander_43 6 GPIO_ACTIVE_LOW>;
-	power-on-gpio = <&gpio_expander_43 2 GPIO_ACTIVE_LOW>;
-	reset-gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>;
-/*	epdev_on-supply = <&reg_wifi>;*/
-
-	fsl,max-link-speed = <1>;
-
-	status = "okay";
-};
-
-&pwm0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_pwm_b>;
-	status = "okay";
-};
-
-&pwm1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_pwm_c>;
-	status = "okay";
-};
-
-&pwm2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_pwm_d>;
-	status = "okay";
-};
-
-&rpmsg{
-	/*
-	 * 64K for one rpmsg instance:
-	 */
-	vdev-nums = <2>;
-	reg = <0x0 0x90000000 0x0 0x20000>;
-	status = "okay";
-};
-
-&sai0 {
-	#sound-dai-cells = <0>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_sai0>;
-	status = "okay";
-};
-
-&tsens {
-	tsens-num = <3>;
-};
-
-&thermal_zones {
-	pmic-thermal0 {
-		polling-delay-passive = <250>;
-		polling-delay = <2000>;
-		thermal-sensors = <&tsens 2>;
-		trips {
-			pmic_alert0: trip0 {
-				temperature = <80000>;
-				hysteresis = <2000>;
-				type = "passive";
-			};
-			pmic_crit0: trip1 {
-				temperature = <125000>;
-				hysteresis = <2000>;
-				type = "critical";
-			};
-		};
-		cooling-maps {
-			map0 {
-				trip = <&pmic_alert0>;
-				cooling-device =
-				<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-			};
-		};
-	};
-};
-
-&usdhc1 {
-	pinctrl-names = "default", "state_100mhz", "state_200mhz";
-	pinctrl-0 = <&pinctrl_usdhc1>;
-	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
-	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
-	bus-width = <8>;
-	non-removable;
-	status = "okay";
-};
-
-&usdhc2 {
-	pinctrl-names = "default", "state_100mhz", "state_200mhz";
-	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
-	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
-	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
-	bus-width = <4>;
-	cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
-	vmmc-supply = <&reg_module_3v3>;
-	status = "okay";
-};
-
-&usbotg1 {
-	extcon = <&extcon_usbc_det &extcon_usbc_det>;
-	vbus-supply = <&reg_usbh_vbus>;
-	srp-disable;
-	hnp-disable;
-	adp-disable;
-	power-polarity-active-high;
-	disable-over-current;
-	status = "okay";
-};
-
-&usbotg3 {
-	dr_mode = "host";
-	status = "okay";
-};
-
-&vpu {
-	status = "disabled";
-};
-
-#ifdef IS_A0_SILICON
-&vpu_decoder {
-	status = "disabled";
-};
-
-&vpu_encoder {
-	status = "disabled";
-};
-#else
-&vpu_decoder {
-	core_type = <1>;
-	status = "okay";
-};
-
-&vpu_encoder {
-	core_type = <1>;
-	status = "okay";
-};
-#endif
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-lvds.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dtsi
index 9beb1431dd0f..582b3a0f65e1 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-lvds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dtsi
@@ -12,15 +12,9 @@
  * GNU General Public License for more details.
  */
 
-/dts-v1/;
-//#define IS_A0_SILICON
-
 #include "fsl-imx8qxp.dtsi"
 
 / {
-	model = "Toradex Colibri iMX8QXP";
-	compatible = "toradex,imx8qxp-colibri", "fsl,imx8qxp";
-
 	aliases {
 		rtc0 = &rtc_i2c;
 		rtc1 = &rtc;
@@ -31,18 +25,6 @@
 		stdout-path = &lpuart3;
 	};
 
-	backlight: backlight {
-		compatible = "pwm-backlight";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_gpio_bl_on>;
-		gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>; /* BKL1_ON */
-		pwms = <&pwm_adma_lcdif 0 100000 0>;
-
-		brightness-levels = <0 4 8 16 32 64 128 255>;
-		default-brightness-level = <6>;
-		status = "okay";
-	};
-
 	extcon_usbc_det: usbc_det {
 		compatible = "linux,extcon-usb-gpio";
 		debounce = <25>;
@@ -105,16 +87,6 @@
 			clocks = <&clk IMX8QXP_AUD_MCLKOUT0>;
 		};
 	};
-
-	lvds1_panel {
-		compatible = "lg,lp156wf1";
-
-		port {
-			panel_lvds1_in: endpoint {
-				remote-endpoint = <&lvds1_out>;
-			};
-		};
-	};
 };
 
 &iomuxc {
@@ -164,7 +136,7 @@
 				SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000020
 				SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
 				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000061
-				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT	0x00000061
+				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT	0x06000061
 				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x00000061
 				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x00000061
 				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x00000061
@@ -756,91 +728,6 @@
 	};
 };
 
-/* DSI/LVDS port 0 */
-&i2c0_mipi_lvds0 {
-	#address-cells = <1>;
-	#size-cells = <0>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>;
-	clock-frequency = <100000>;
-	status = "disabled";
-};
-
-&ldb1_phy {
-	status = "okay";
-};
-
-&ldb1 {
-	status = "okay";
-	fsl,dual-channel;
-	power-domains = <&pd_mipi_dsi_1_dual_lvds>;
-
-	lvds-channel@0 {
-		fsl,data-mapping = "jeida";
-		fsl,data-width = <24>; /* Actually would need 18 but isn't supported by the driver */
-		status = "okay";
-
-		port@1 {
-			reg = <1>;
-
-			lvds1_out: endpoint {
-				remote-endpoint = <&panel_lvds1_in>;
-			};
-		};
-	};
-};
-
-&mipi_dsi_phy1 {
-	status = "okay";
-};
-
-&mipi_dsi1 {
-	pwr-delay = <10>;
-	status = "okay";
-};
-
-&mipi_dsi_bridge1 {
-	status = "disabled";
-};
-
-/* DSI/LVDS port 1 */
-&i2c0_mipi_lvds1 {
-	#address-cells = <1>;
-	#size-cells = <0>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>;
-	clock-frequency = <100000>;
-	status = "disabled";
-};
-
-&ldb2_phy {
-	status = "okay";
-};
-
-&ldb2 {
-	status = "disabled";
-};
-
-&mipi_dsi_phy2 {
-	status = "okay";
-};
-
-&mipi_dsi2 {
-	pwr-delay = <10>;
-	status = "okay";
-};
-
-&mipi_dsi_bridge2 {
-	status = "disabled";
-};
-
-
-&pwm_adma_lcdif {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_pwm_a>;
-	status = "okay";
-};
-
 &lpspi2 {
 	#address-cells = <1>;
 	#size-cells = <0>;
@@ -874,6 +761,12 @@
 	status = "okay";
 };
 
+&pwm_adma_lcdif {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm_a>;
+	status = "okay";
+};
+
 &pwm0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pwm_b>;
@@ -990,11 +883,12 @@
 };
 #else
 &vpu_decoder {
+	core_type = <1>;
 	status = "okay";
 };
 
 &vpu_encoder {
+	core_type = <1>;
 	status = "okay";
 };
 #endif
-
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-lvds-dual-eval-v3.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-lvds-dual-eval-v3.dts
new file mode 100644
index 000000000000..19e2991d99fd
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-lvds-dual-eval-v3.dts
@@ -0,0 +1,125 @@
+/*
+ * Copyright (C) 2018, Toradex AG
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+//#define IS_A0_SILICON
+
+#include "fsl-imx8qxp-colibri-eval-v3.dtsi"
+
+/ {
+	model = "Toradex Colibri iMX8QXP with dual channel lvds";
+	compatible = "toradex,imx8qxp-colibri-lvds-dual", "toradex,imx8qxp-colibri", "fsl,imx8qxp";
+
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_bl_on>;
+		gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>; /* BKL1_ON */
+		pwms = <&pwm_adma_lcdif 0 100000 0>;
+
+		brightness-levels = <0 4 8 16 32 64 128 255>;
+		default-brightness-level = <6>;
+		status = "okay";
+	};
+
+
+	lvds1_panel {
+		compatible = "lg,lp156wf1";
+
+		port {
+			panel_lvds1_in: endpoint {
+				remote-endpoint = <&lvds1_out>;
+			};
+		};
+	};
+};
+
+/* DSI/LVDS port 0 */
+&i2c0_mipi_lvds0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>;
+	clock-frequency = <100000>;
+	status = "disabled";
+};
+
+&ldb1_phy {
+	status = "okay";
+};
+
+&ldb1 {
+	status = "okay";
+	fsl,dual-channel;
+	power-domains = <&pd_mipi_dsi_1_dual_lvds>;
+
+	lvds-channel@0 {
+		fsl,data-mapping = "jeida";
+		fsl,data-width = <24>; /* Actually would need 18 but isn't supported by the driver */
+		status = "okay";
+
+		port@1 {
+			reg = <1>;
+
+			lvds1_out: endpoint {
+				remote-endpoint = <&panel_lvds1_in>;
+			};
+		};
+	};
+};
+
+&mipi_dsi_phy1 {
+	status = "okay";
+};
+
+&mipi_dsi1 {
+	pwr-delay = <10>;
+	status = "okay";
+};
+
+&mipi_dsi_bridge1 {
+	status = "disabled";
+};
+
+/* DSI/LVDS port 1 */
+&i2c0_mipi_lvds1 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>;
+	clock-frequency = <100000>;
+	status = "disabled";
+};
+
+&ldb2_phy {
+	status = "okay";
+};
+
+&ldb2 {
+	status = "disabled";
+};
+
+&mipi_dsi_phy2 {
+	status = "okay";
+};
+
+&mipi_dsi2 {
+	pwr-delay = <10>;
+	status = "okay";
+};
+
+&mipi_dsi_bridge2 {
+	status = "disabled";
+};
+