diff options
| author | Max Krummenacher <max.krummenacher@toradex.com> | 2018-10-11 21:12:23 +0200 |
|---|---|---|
| committer | Max Krummenacher <max.krummenacher@toradex.com> | 2018-11-08 11:31:58 +0100 |
| commit | 4f6912ebe45e898eaa2732e748ad1a26331a0e7e (patch) | |
| tree | 92b5c8e824800f877fa03ba2499cc0a9aaf80080 | |
| parent | 3638220a056b0d99f5dbd64b1178b37a3962e054 (diff) | |
fsl-imx8dx.dtsi: lpspi2: add node
While at it set the assigned clock to 24 MHz, as that it what results with
the 20 MHz currently used.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi index 051a85e6d826..e88634fd1a96 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi @@ -2610,11 +2610,25 @@ <&clk IMX8QXP_SPI0_IPG_CLK>; clock-names = "per", "ipg"; assigned-clocks = <&clk IMX8QXP_SPI0_CLK>; - assigned-clock-rates = <20000000>; + assigned-clock-rates = <24000000>; power-domains = <&pd_dma_lpspi0>; status = "disabled"; }; + lpspi2: lpspi@5a020000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x0 0x5a020000 0x0 0x10000>; + interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_SPI2_CLK>, + <&clk IMX8QXP_SPI2_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_SPI2_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpspi2>; + status = "disabled"; + }; + lpuart0: serial@5a060000 { compatible = "fsl,imx8qm-lpuart"; reg = <0x0 0x5a060000 0x0 0x1000>; |