diff options
| author | Max Krummenacher <max.krummenacher@toradex.com> | 2018-09-11 14:33:52 +0200 |
|---|---|---|
| committer | Max Krummenacher <max.krummenacher@toradex.com> | 2018-11-08 20:10:05 +0100 |
| commit | adbc382a81d906a9b27a9a184af6b6491451dec2 (patch) | |
| tree | 8e408da3fa53555e785b36db066dfab6c4fd4622 | |
| parent | c4fbc7617d3a6d595a7415e1c618019a39cdc32d (diff) | |
imx8x: inital failing try to bringup pwm
Copy the pwm definitions from imx8qm to fsl-imx8dx.dtsi.
Enable it in the device tree.
Without the power domain property nothing happens when playing in /sys/class/pwm.
With it you get a kernel Oops.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi | 98 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dts | 2 |
2 files changed, 99 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi index e88634fd1a96..7e047370057d 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi @@ -2573,6 +2573,104 @@ power-domains = <&pd_mipi_csi>; }; + pwm0: pwm@5d000000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d000000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM0_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM0_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM0_HF_CLK>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm0>; + status = "disabled"; + }; + +#if 0 + pwm1: pwm@5d010000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d010000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM1_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM1_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM1_HF_CLK>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm2: pwm@5d020000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d020000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM2_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM2_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM2_HF_CLK>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm3: pwm@5d030000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d030000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM3_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM3_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM3_HF_CLK>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm4: pwm@5d040000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d040000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM4_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM4_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM4_HF_CLK>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm5: pwm@5d050000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d050000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM5_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM5_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM5_HF_CLK>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm6: pwm@5d060000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d060000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM6_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM6_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM6_HF_CLK>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm7: pwm@5d070000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d070000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM7_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM7_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM7_HF_CLK>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + status = "disabled"; + }; +#endif gpu_3d0: gpu@53100000 { compatible = "fsl,imx8-gpu"; reg = <0x0 0x53100000 0 0x40000>; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dts index 3844a09b64f0..530acfcde0ff 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dts @@ -237,7 +237,6 @@ fsl,pins = < SC_P_CSI_D04_CI_PI_D06 0x00000061 SC_P_UART1_RTS_B_LSIO_PWM2_OUT 0x00000060 - >; }; @@ -712,6 +711,7 @@ &pwm0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm_b>; + status = "okay"; }; &pwm1 { |