diff options
| author | Max Krummenacher <max.krummenacher@toradex.com> | 2018-10-11 20:06:24 +0200 |
|---|---|---|
| committer | Max Krummenacher <max.krummenacher@toradex.com> | 2018-11-08 20:10:04 +0100 |
| commit | c4fbc7617d3a6d595a7415e1c618019a39cdc32d (patch) | |
| tree | 1fb79dffc406d17fdd47e298dfcfe322d2b61327 | |
| parent | b72e320407f1fe83fa0f09a414c5f963326fa455 (diff) | |
fsl-imx8qxp-colibri-eval-v3.dts: add lcdif pingroup
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dts | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dts index 9f9bfc3faff0..3844a09b64f0 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dts @@ -282,6 +282,37 @@ >; }; + pinctrl_lcdif: lcdif-pins { + fsl,pins = < + SC_P_MCLK_OUT0_ADMA_LCDIF_CLK 0x00000060 + SC_P_SPI3_CS0_ADMA_LCDIF_HSYNC 0x00000060 + SC_P_MCLK_IN0_ADMA_LCDIF_VSYNC 0x00000060 + SC_P_MCLK_IN1_ADMA_LCDIF_EN 0x00000060 + SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000060 + + SC_P_ESAI0_FSR_ADMA_LCDIF_D00 0x00000060 + SC_P_USDHC1_WP_LSIO_GPIO4_IO21 0x00000060 + SC_P_ESAI0_FST_ADMA_LCDIF_D01 0x00000060 + SC_P_ESAI0_SCKR_ADMA_LCDIF_D02 0x00000060 + SC_P_ESAI0_SCKT_ADMA_LCDIF_D03 0x00000060 + SC_P_ESAI0_TX0_ADMA_LCDIF_D04 0x00000060 + SC_P_ESAI0_TX1_ADMA_LCDIF_D05 0x00000060 + SC_P_ESAI0_TX2_RX3_ADMA_LCDIF_D06 0x00000060 + SC_P_ESAI0_TX3_RX2_ADMA_LCDIF_D07 0x00000060 + SC_P_ESAI0_TX4_RX1_ADMA_LCDIF_D08 0x00000060 + SC_P_ESAI0_TX5_RX0_ADMA_LCDIF_D09 0x00000060 + SC_P_SPDIF0_RX_ADMA_LCDIF_D10 0x00000060 + SC_P_SPDIF0_TX_ADMA_LCDIF_D11 0x00000060 + SC_P_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 0x00000060 + SC_P_SPI3_SCK_ADMA_LCDIF_D13 0x00000060 + SC_P_SPI3_SDO_ADMA_LCDIF_D14 0x00000060 + SC_P_SPI3_SDI_ADMA_LCDIF_D15 0x00000060 + SC_P_SPI3_CS1_ADMA_LCDIF_D16 0x00000060 + SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x00000060 + SC_P_UART1_CTS_B_ADMA_LCDIF_D17 0x00000060 + >; + }; + pinctrl_usbh1_reg: usbh1-reg { fsl,pins = < SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000040 |