MLK-18789-5: ARM64: dts: imx8dx: Add dts file for lcdif

Add nodes for the ADMA eLCDIF controller found in i.MX8QXP and specific
dts file for it's usage with the Seiko 43WVF1G LCD panel.

Signed-off-by: Robert Chiras <robert.chiras@nxp.com>

4 files changed, 185 insertions, 14 deletions

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 7a244a59370c..5f70e5418e6b 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -51,6 +51,7 @@ dtb-$(CONFIG_ARCH_FSL_IMX8QXP) += fsl-imx8qxp-lpddr4-arm2.dtb \
 				  fsl-imx8qxp-mek-enet2-tja1100.dtb \
 				  fsl-imx8qxp-mek-dsi-rm67191.dtb \
 				  fsl-imx8qxp-mek-a0.dtb \
+				  fsl-imx8qxp-mek-lcdif.dtb \
 				  fsl-imx8qxp-mek-it6263-lvds0-dual-channel.dtb \
 				  fsl-imx8qxp-mek-it6263-lvds1-dual-channel.dtb \
 				  fsl-imx8qxp-mek-jdi-wuxga-lvds0-panel.dtb \
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi
index 7e047370057d..6baac97daed4 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi
@@ -818,6 +818,20 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 
+			pd_dma_elcdif_pll: PD_DMA_ELCDIF_PLL {
+				reg = <SC_R_ELCDIF_PLL>;
+				#power-domain-cells = <0>;
+				power-domains = <&pd_dma>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				pd_dma_lcd0: PD_DMA_LCD_0 {
+					reg = <SC_R_LCD_0>;
+					#power-domain-cells = <0>;
+					power-domains = <&pd_dma_elcdif_pll>;
+				};
+			};
+
 			pd_dma_flexcan0: PD_DMA_CAN_0 {
 				reg = <SC_R_CAN_0>;
 				#power-domain-cells = <0>;
@@ -979,20 +993,6 @@
 				#power-domain-cells = <0>;
 				power-domains = <&pd_dma>;
 			};
-
-			pd_dma_elcdif_pll: PD_DMA_ELCDIF_PLL {
-				reg = <SC_R_ELCDIF_PLL>;
-				#power-domain-cells = <0>;
-				power-domains = <&pd_dma>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				pd_dma_lcd0: PD_DMA_LCD_0 {
-					reg = <SC_R_LCD_0>;
-					#power-domain-cells = <0>;
-					power-domains = <&pd_dma_elcdif_pll>;
-				};
-			};
 		};
 
 		pd_gpu: gpu-power-domain {
@@ -1737,6 +1737,32 @@
 		power-domains = <&pd_mipi_dsi0>;
 	};
 
+	adma_lcdif: lcdif@5a180000 {
+		compatible = "fsl,imx8qxp-lcdif", "fsl,imx28-lcdif";
+		reg = <0x0 0x5a180000 0x0 0x10000>;
+		clocks = <&clk IMX8QXP_LCD_CLK>, <&clk IMX8QXP_LCD_IPG_CLK>;
+		clock-names = "pix", "disp_axi";
+		assigned-clocks = <&clk IMX8QXP_LCD_SEL>, <&clk IMX8QXP_ELCDIF_PLL>;
+		assigned-clock-rates = <804000000>, <804000000>;
+		assigned-clock-parents = <&clk IMX8QXP_ELCDIF_PLL>;
+		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+		power-domains = <&pd_dma_lcd0>;
+		status = "disabled";
+	};
+
+	pwm_adma_lcdif: pwm@5a190000 {
+		compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
+		reg = <0x0 0x5a190000 0 0x1000>;
+		clocks = <&clk IMX8QXP_PWM_IPG_CLK>,
+			 <&clk IMX8QXP_PWM_CLK>;
+		clock-names = "ipg", "per";
+		assigned-clocks = <&clk IMX8QXP_PWM_CLK>;
+		assigned-clock-rates = <24000000>;
+		#pwm-cells = <2>;
+		power-domains = <&pd_dma_pwm0>;
+		status = "disabled";
+	};
+
 	mipi_dsi_csr1: csr@56221000 {
 		compatible = "fsl,imx8qxp-mipi-dsi-csr", "syscon";
 		reg = <0x0 0x56221000 0x0 0x1000>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-lcdif.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-lcdif.dts
new file mode 100644
index 000000000000..750d725ee990
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek-lcdif.dts
@@ -0,0 +1,85 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "fsl-imx8qxp-mek.dts"
+
+/ {
+	display-subsystem {
+		status = "disabled";
+	};
+
+	panel {
+		compatible = "sii,43wvf1g";
+		backlight = <&lcdif_backlight>;
+
+		port {
+			panel_in: endpoint {
+				remote-endpoint = <&adapter_out>;
+			};
+		};
+	};
+
+	seiko_adapter: seiko-adapter {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "nxp,seiko-43wvfig";
+		bus_mode = <18>;
+
+		port@0 {
+			reg = <0>;
+			adapter_in: endpoint {
+				remote-endpoint = <&lcdif_out>;
+			};
+		};
+		port@1 {
+			reg = <1>;
+			adapter_out: endpoint {
+				remote-endpoint = <&panel_in>;
+			};
+		};
+	};
+
+};
+
+&esai0 {
+	status = "disabled";
+};
+
+&sai1 {
+	status = "disabled";
+};
+
+&lpuart1 {
+	status = "disabled";
+};
+
+&lcdif_backlight {
+	status = "okay";
+};
+
+&adma_lcdif {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lcdif>;
+	status = "okay";
+
+	port@0 {
+		lcdif_out: lcdif-endpoint {
+			remote-endpoint = <&adapter_in>;
+		};
+	};
+};
+
+&pwm_adma_lcdif {
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts
index a215f719dabf..069532503231 100755
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-mek.dts
@@ -198,6 +198,16 @@
 				    100>;
 		default-brightness-level = <80>;
 	};
+
+	lcdif_backlight: lcdif_backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm_adma_lcdif 0 100000 0>;
+
+		brightness-levels = <0 4 8 16 32 64 128 255>;
+		default-brightness-level = <6>;
+		status = "disabled";
+	};
+
 };
 
 &acm {
@@ -260,7 +270,9 @@
 	imx8qxp-mek {
 		pinctrl_hog: hoggrp {
 			fsl,pins = <
+				/* TODO: conflicts with LCDIF!!!
 				SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0	0x0600004c
+				 */
 				SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD	0x000514a0
 			>;
 		};
@@ -369,6 +381,46 @@
 			>;
 		};
 
+		pinctrl_lcdif: lcdif_grp {
+			fsl,pins = <
+				SC_P_ESAI0_FSR_ADMA_LCDIF_D00		0x00000060
+				SC_P_ESAI0_FST_ADMA_LCDIF_D01		0x00000060
+				SC_P_ESAI0_SCKR_ADMA_LCDIF_D02		0x00000060
+				SC_P_ESAI0_SCKT_ADMA_LCDIF_D03		0x00000060
+				SC_P_ESAI0_TX0_ADMA_LCDIF_D04		0x00000060
+				SC_P_ESAI0_TX1_ADMA_LCDIF_D05		0x00000060
+				SC_P_ESAI0_TX2_RX3_ADMA_LCDIF_D06	0x00000060
+				SC_P_ESAI0_TX3_RX2_ADMA_LCDIF_D07	0x00000060
+				SC_P_ESAI0_TX4_RX1_ADMA_LCDIF_D08	0x00000060
+				SC_P_ESAI0_TX5_RX0_ADMA_LCDIF_D09	0x00000060
+				SC_P_SPDIF0_RX_ADMA_LCDIF_D10		0x00000060
+				SC_P_SPDIF0_TX_ADMA_LCDIF_D11		0x00000060
+				SC_P_SPDIF0_EXT_CLK_ADMA_LCDIF_D12	0x00000060
+				SC_P_SPI3_SCK_ADMA_LCDIF_D13		0x00000060
+				SC_P_SPI3_SDO_ADMA_LCDIF_D14		0x00000060
+				SC_P_SPI3_SDI_ADMA_LCDIF_D15		0x00000060
+				SC_P_UART1_RTS_B_ADMA_LCDIF_D16		0x00000060
+				SC_P_UART1_CTS_B_ADMA_LCDIF_D17		0x00000060
+				SC_P_SAI0_TXD_ADMA_LCDIF_D18		0x00000060
+				SC_P_SAI0_TXC_ADMA_LCDIF_D19		0x00000060
+				SC_P_SAI0_RXD_ADMA_LCDIF_D20		0x00000060
+				SC_P_SAI1_RXD_ADMA_LCDIF_D21		0x00000060
+				SC_P_SAI1_RXC_ADMA_LCDIF_D22		0x00000060
+				SC_P_SAI1_RXFS_ADMA_LCDIF_D23		0x00000060
+				SC_P_SPI3_CS0_ADMA_LCDIF_HSYNC		0x00000060
+				SC_P_SPI3_CS1_ADMA_LCDIF_RESET		0x00000060
+				SC_P_MCLK_IN1_ADMA_LCDIF_EN		0x00000060
+				SC_P_MCLK_IN0_ADMA_LCDIF_VSYNC		0x00000060
+				SC_P_MCLK_OUT0_ADMA_LCDIF_CLK		0x00000060
+			>;
+		};
+
+		pinctrl_lcdif_pwm: lcdif_pwm_grp {
+			fsl,pins = <
+				SC_P_SPI0_CS1_ADMA_LCD_PWM0_OUT		0x00000060
+			>;
+		};
+
 		pinctrl_flexspi0: flexspi0grp {
 			fsl,pins = <
 				SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0	0x0600004c
@@ -1145,6 +1197,13 @@
 	status = "okay";
 };
 
+&pwm_adma_lcdif {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lcdif_pwm>;
+	status = "okay";
+};
+
+
 /* DSI/LVDS port 1 */
 &i2c0_mipi_lvds1 {
 	#address-cells = <1>;