diff options
| author | Stefan Agner <stefan.agner@toradex.com> | 2018-02-19 16:41:49 +0100 |
|---|---|---|
| committer | Stefan Agner <stefan.agner@toradex.com> | 2018-02-19 16:41:49 +0100 |
| commit | 5d3e6620b685fe06d69479623f52264361ad26e0 (patch) | |
| tree | b554571757a895a7c975174627f389fa2159ff27 | |
| parent | a0b0515b3992b6361514a3c18740864321b5bf50 (diff) | |
apalis-imx8qm: mux clock enable pin in clock driver
Make sure that the clock enable pin is assigned to the GPIO
clock driver.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts index 160f4f97629e..10e9063be16c 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts @@ -44,6 +44,8 @@ pcie_sata_refclk_gate: ref-clock { compatible = "gpio-gate-clock"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_sata_refclk>; #clock-cells = <0>; clocks = <&pcie_sata_refclk>; enable-gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>; @@ -327,9 +329,14 @@ >; }; - pinctrl_pciea: pcieagrp{ + pinctrl_pcie_sata_refclk: pciesatarefclkgrp { fsl,pins = < SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x00000021 + >; + }; + + pinctrl_pciea: pcieagrp{ + fsl,pins = < SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x00000021 SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x00000021 SC_P_MLB_SIG_LSIO_GPIO3_IO26 0x00000021 |