MLK-17344-2: ARM64: dts: add constraint-rate for hdmi of imx8qm

In imx8qm the hdmi audio sound is breaking from time to time, the
reason is that the DPLL jitter issue cause that HDMI can't lock
this clock internally, that some audio data is dropped. It is
hardware issue, here we add software workaround.

We tried two method:
1. Changed Audio PLL setting to use non-fractional multiplier
(768MHz=24MHz*32). This setting is significantly improving HDMI Audio
but audio is still breaking from time to time.
2. Generated HDMI TX audio clock from external audio codec
(24MHz clock => SLSlice[0] => MCLKOUT => External CODEC ref clock to PLL
=> ESAI Audio clock => loopback to HDMI TX SAI => HDMI TX).
HDMI TX audio is clear.

The second method depends on external codec, for we want to keep
the independence of driver, so we use the method 1.

For method 1, we need to set a dedicate rate for HDMI, we use the
AUDIO_PLL1, but which is conflict with AMIX, so we disable AMIX in
hdmi dts and only support 48kHz for HDMI audio

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>

1 files changed, 22 insertions, 5 deletions

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-hdmi.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-hdmi.dts
index f7129850081c..be4e300bb358 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-hdmi.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-hdmi.dts
@@ -22,8 +22,13 @@
 		compatible = "fsl,imx-audio-cdnhdmi";
 		model = "imx-audio-hdmi";
 		audio-cpu = <&sai_hdmi_tx>;
+		constraint-rate = <48000>;
 		protocol = <1>;
 	};
+
+	sound-amix-sai {
+		status = "disabled";
+	};
 };
 
 &ldb1_phy {
@@ -43,14 +48,26 @@
 	status = "okay";
 };
 
+&amix {
+	status = "disabled";
+};
+
+&sai6 {
+	status = "disabled";
+};
+
+&sai7 {
+	status = "disabled";
+};
+
 &sai_hdmi_tx {
 	assigned-clocks =<&clk IMX8QM_ACM_HDMI_TX_SAI0_MCLK_SEL>,
-			<&clk IMX8QM_AUD_PLL0_DIV>,
-			<&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>,
-			<&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>,
+			<&clk IMX8QM_AUD_PLL1_DIV>,
+			<&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_DIV>,
+			<&clk IMX8QM_AUD_ACM_AUD_REC_CLK1_DIV>,
 			<&clk IMX8QM_AUD_SAI_HDMITX0_MCLK>;
-	assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>;
-	assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>;
+	assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>;
+	assigned-clock-rates = <0>, <768000000>, <768000000>, <768000000>, <768000000>;
 	fsl,sai-asynchronous;
 	status = "okay";
 };