diff options
| author | Francesco Dolcini <francesco.dolcini@toradex.com> | 2023-04-19 19:24:14 +0200 |
|---|---|---|
| committer | Francesco Dolcini <francesco.dolcini@toradex.com> | 2023-04-28 14:38:22 +0200 |
| commit | 75c2323cabf9f35cee2731a93c1e421b73886f49 (patch) | |
| tree | f96c4a36f7172a270713c32fcbe0e935989bc7b1 | |
| parent | db6c6870a9baa0324354b5362daae7d3da428645 (diff) | |
drm/bridge: tc358768: fix PLL parameters computation
According to Toshiba documentation the PLL input clock after the divider
should be not less than 4MHz, fix the PLL parameters computation
accordingly.
Upstream-Status: Submitted [https://lore.kernel.org/all/20230427142934.55435-1-francesco@dolcini.it/]
Fixes: ff1ca6397b1d ("drm/bridge: Add tc358768 driver")
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
| -rw-r--r-- | drivers/gpu/drm/bridge/tc358768.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc358768.c index 25624b0ed078..4a0ecf33b47b 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -335,13 +335,17 @@ static int tc358768_calc_pll(struct tc358768_priv *priv, u32 fbd; for (fbd = 0; fbd < 512; ++fbd) { - u32 pll, diff; + u32 pll, diff, pll_in; pll = (u32)div_u64((u64)refclk * (fbd + 1), divisor); if (pll >= max_pll || pll < min_pll) continue; + pll_in = (u32)div_u64((u64)refclk, prd + 1); + if (pll_in < 4000000) + continue; + diff = max(pll, target_pll) - min(pll, target_pll); if (diff < best_diff) { |