diff options
| author | Dmitry Osipenko <digetx@gmail.com> | 2021-10-03 02:34:45 +0300 |
|---|---|---|
| committer | Francesco Dolcini <francesco.dolcini@toradex.com> | 2023-03-22 11:54:49 +0100 |
| commit | d4b91b3385639ae7749367ac1cce9b551c187409 (patch) | |
| tree | 28cf381a2937532acc8f46eae387c5cedf97909a | |
| parent | c3b173c3c986903a0fe19890d2692bf64c2e2619 (diff) | |
drm/bridge: tc358768: Calculate video start delay
Calculate video start delay based on the display timing instead
of hardcoding it to a default value. This fixes "trembling" display
output on Asus Transformer TF700T which uses Panasonic VVX10F004B00
display panel.
Upstream-Status: Backport [b93e947664a1a63a3e6cb5d94f38d5579e41d951]
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # Asus TF700T
Tested-by: Maxim Schwalm <maxim.schwalm@gmail.com> #TF700T
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Robert Foss <robert.foss@linaro.org>
Signed-off-by: Robert Foss <robert.foss@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20211002233447.1105-4-digetx@gmail.com
| -rw-r--r-- | drivers/gpu/drm/bridge/tc358768.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/tc358768.c index a5be529037c3..76cc35e3c964 100644 --- a/drivers/gpu/drm/bridge/tc358768.c +++ b/drivers/gpu/drm/bridge/tc358768.c @@ -634,7 +634,8 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) u32 val, val2, lptxcnt, hact, data_type; const struct drm_display_mode *mode; u32 dsibclk_nsk, dsiclk_nsk, ui_nsk, phy_delay_nsk; - u32 dsiclk, dsibclk; + u32 dsiclk, dsibclk, video_start; + const u32 internal_delay = 40; int ret, i; tc358768_hw_enable(priv); @@ -663,23 +664,27 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) case MIPI_DSI_FMT_RGB888: val |= (0x3 << 4); hact = mode->hdisplay * 3; + video_start = (mode->htotal - mode->hsync_start) * 3; data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24; break; case MIPI_DSI_FMT_RGB666: val |= (0x4 << 4); hact = mode->hdisplay * 3; + video_start = (mode->htotal - mode->hsync_start) * 3; data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18; break; case MIPI_DSI_FMT_RGB666_PACKED: val |= (0x4 << 4) | BIT(3); hact = mode->hdisplay * 18 / 8; + video_start = (mode->htotal - mode->hsync_start) * 18 / 8; data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18; break; case MIPI_DSI_FMT_RGB565: val |= (0x5 << 4); hact = mode->hdisplay * 2; + video_start = (mode->htotal - mode->hsync_start) * 2; data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16; break; default: @@ -690,7 +695,8 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) } /* VSDly[9:0] */ - tc358768_write(priv, TC358768_VSDLY, 1); + video_start = max(video_start, internal_delay + 1) - internal_delay; + tc358768_write(priv, TC358768_VSDLY, video_start); tc358768_write(priv, TC358768_DATAFMT, val); tc358768_write(priv, TC358768_DSITX_DT, data_type); |