ENGR00177716 i.mx Sabreauto : SD Card on Mainboard initialisation and read error

SD Card in main board takes a long route hence with Drive Speed High 80 OHMS
causing error. Per suggestion DSE 40 OHMS is used.

Signed-off-by: Prabhu Sundararaj <b36876@freescale.com>

4 files changed, 44 insertions, 12 deletions

diff --git a/arch/arm/mach-mx6/board-mx6q_sabreauto.h b/arch/arm/mach-mx6/board-mx6q_sabreauto.h
index 8bc3705f8746..076ca9c3b727 100644
--- a/arch/arm/mach-mx6/board-mx6q_sabreauto.h
+++ b/arch/arm/mach-mx6/board-mx6q_sabreauto.h
@@ -64,12 +64,12 @@ static iomux_v3_cfg_t mx6q_sabreauto_pads[] = {
 	MX6Q_PAD_DISP0_DAT20__GPIO_5_14, /* vol down */
 
 	/* SD1 */
-	MX6Q_PAD_SD1_CLK__USDHC1_CLK,
-	MX6Q_PAD_SD1_CMD__USDHC1_CMD,
-	MX6Q_PAD_SD1_DAT0__USDHC1_DAT0,
-	MX6Q_PAD_SD1_DAT1__USDHC1_DAT1,
-	MX6Q_PAD_SD1_DAT2__USDHC1_DAT2,
-	MX6Q_PAD_SD1_DAT3__USDHC1_DAT3,
+	MX6Q_PAD_SD1_CLK__USDHC1_CLK_50MHZ_40OHM,
+	MX6Q_PAD_SD1_CMD__USDHC1_CMD_50MHZ_40OHM,
+	MX6Q_PAD_SD1_DAT0__USDHC1_DAT0_50MHZ_40OHM,
+	MX6Q_PAD_SD1_DAT1__USDHC1_DAT1_50MHZ_40OHM,
+	MX6Q_PAD_SD1_DAT2__USDHC1_DAT2_50MHZ_40OHM,
+	MX6Q_PAD_SD1_DAT3__USDHC1_DAT3_50MHZ_40OHM,
 
 	/* SD1_CD and SD1_WP */
 	MX6Q_PAD_GPIO_1__GPIO_1_1,
diff --git a/arch/arm/mach-mx6/board-mx6solo_sabreauto.h b/arch/arm/mach-mx6/board-mx6solo_sabreauto.h
index ba293141ac24..17d7313900f0 100644
--- a/arch/arm/mach-mx6/board-mx6solo_sabreauto.h
+++ b/arch/arm/mach-mx6/board-mx6solo_sabreauto.h
@@ -65,12 +65,12 @@ static iomux_v3_cfg_t mx6dl_sabreauto_pads[] = {
 	MX6DL_PAD_DISP0_DAT20__GPIO_5_14, /* vol down */
 
 	/* SD1 */
-	MX6DL_PAD_SD1_CLK__USDHC1_CLK,
-	MX6DL_PAD_SD1_CMD__USDHC1_CMD,
-	MX6DL_PAD_SD1_DAT0__USDHC1_DAT0,
-	MX6DL_PAD_SD1_DAT1__USDHC1_DAT1,
-	MX6DL_PAD_SD1_DAT2__USDHC1_DAT2,
-	MX6DL_PAD_SD1_DAT3__USDHC1_DAT3,
+	MX6DL_PAD_SD1_CLK__USDHC1_CLK_50MHZ_40OHM,
+	MX6DL_PAD_SD1_CMD__USDHC1_CMD_50MHZ_40OHM,
+	MX6DL_PAD_SD1_DAT0__USDHC1_DAT0_50MHZ_40OHM,
+	MX6DL_PAD_SD1_DAT1__USDHC1_DAT1_50MHZ_40OHM,
+	MX6DL_PAD_SD1_DAT2__USDHC1_DAT2_50MHZ_40OHM,
+	MX6DL_PAD_SD1_DAT3__USDHC1_DAT3_50MHZ_40OHM,
 
 	/* SD1_CD and SD1_WP */
 	MX6DL_PAD_GPIO_1__GPIO_1_1,
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx6dl.h b/arch/arm/plat-mxc/include/mach/iomux-mx6dl.h
index 918dc58b57f8..650a0e791bee 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx6dl.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx6dl.h
@@ -42,6 +42,10 @@
 		PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |		\
 		PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
+#define MX6DL_USDHC_PAD_CTRL_50MHZ_40OHM (PAD_CTL_PKE | PAD_CTL_PUE |		\
+		PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |		\
+		PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
 #define MX6DL_USDHC_PAD_CTRL_100MHZ (PAD_CTL_PKE | PAD_CTL_PUE |	\
 		PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_MED |		\
 		PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
@@ -3195,6 +3199,8 @@
 
 #define MX6DL_PAD_SD1_CLK__USDHC1_CLK                                          \
 		IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0928, 1, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_SD1_CLK__USDHC1_CLK_50MHZ_40OHM                              \
+		IOMUX_PAD(0x06C4, 0x02DC, 0, 0x0928, 1, MX6DL_USDHC_PAD_CTRL_50MHZ_40OHM)
 #define MX6DL_PAD_SD1_CLK__OSC32K_32K_OUT                                      \
 		IOMUX_PAD(0x06C4, 0x02DC, 2, 0x0000, 0, NO_PAD_CTRL)
 #define MX6DL_PAD_SD1_CLK__GPT_CLKIN                                           \
@@ -3206,6 +3212,8 @@
 
 #define MX6DL_PAD_SD1_CMD__USDHC1_CMD                                          \
 		IOMUX_PAD(0x06C8, 0x02E0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_SD1_CMD__USDHC1_CMD_50MHZ_40OHM                              \
+		IOMUX_PAD(0x06C8, 0x02E0, 0 | IOMUX_CONFIG_SION, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_50MHZ_40OHM)
 #define MX6DL_PAD_SD1_CMD__PWM4_PWMO                                           \
 		IOMUX_PAD(0x06C8, 0x02E0, 2, 0x0000, 0, NO_PAD_CTRL)
 #define MX6DL_PAD_SD1_CMD__GPT_CMPOUT1                                         \
@@ -3217,6 +3225,8 @@
 
 #define MX6DL_PAD_SD1_DAT0__USDHC1_DAT0                                        \
 		IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_SD1_DAT0__USDHC1_DAT0_50MHZ_40OHM                            \
+		IOMUX_PAD(0x06CC, 0x02E4, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_50MHZ_40OHM)
 #define MX6DL_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS                           \
 		IOMUX_PAD(0x06CC, 0x02E4, 2, 0x0000, 0, NO_PAD_CTRL)
 #define MX6DL_PAD_SD1_DAT0__GPT_CAPIN1                                         \
@@ -3232,6 +3242,8 @@
 
 #define MX6DL_PAD_SD1_DAT1__USDHC1_DAT1                                        \
 		IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_SD1_DAT1__USDHC1_DAT1_50MHZ_40OHM                            \
+		IOMUX_PAD(0x06D0, 0x02E8, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_50MHZ_40OHM)
 #define MX6DL_PAD_SD1_DAT1__PWM3_PWMO                                          \
 		IOMUX_PAD(0x06D0, 0x02E8, 2, 0x0000, 0, NO_PAD_CTRL)
 #define MX6DL_PAD_SD1_DAT1__GPT_CAPIN2                                         \
@@ -3247,6 +3259,8 @@
 
 #define MX6DL_PAD_SD1_DAT2__USDHC1_DAT2                                        \
 		IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_SD1_DAT2__USDHC1_DAT2_50MHZ_40OHM                            \
+		IOMUX_PAD(0x06D4, 0x02EC, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_50MHZ_40OHM)
 #define MX6DL_PAD_SD1_DAT2__GPT_CMPOUT2                                        \
 		IOMUX_PAD(0x06D4, 0x02EC, 2, 0x0000, 0, NO_PAD_CTRL)
 #define MX6DL_PAD_SD1_DAT2__PWM2_PWMO                                          \
@@ -3262,6 +3276,8 @@
 
 #define MX6DL_PAD_SD1_DAT3__USDHC1_DAT3                                        \
 		IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL)
+#define MX6DL_PAD_SD1_DAT3__USDHC1_DAT3_50MHZ_40OHM                            \
+		IOMUX_PAD(0x06D8, 0x02F0, 0, 0x0000, 0, MX6DL_USDHC_PAD_CTRL_50MHZ_40OHM)
 #define MX6DL_PAD_SD1_DAT3__GPT_CMPOUT3                                        \
 		IOMUX_PAD(0x06D8, 0x02F0, 2, 0x0000, 0, NO_PAD_CTRL)
 #define MX6DL_PAD_SD1_DAT3__PWM1_PWMO                                          \
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx6q.h b/arch/arm/plat-mxc/include/mach/iomux-mx6q.h
index c6b932e7fe6c..6febfeb8fc80 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx6q.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx6q.h
@@ -58,6 +58,10 @@ typedef enum iomux_config {
 		PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |	\
 		PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
 
+#define MX6Q_USDHC_PAD_CTRL_50MHZ_40OHM (PAD_CTL_PKE | PAD_CTL_PUE |		\
+		PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |		\
+		PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
 #define MX6Q_USDHC_PAD_CTRL_100MHZ	(PAD_CTL_PKE | PAD_CTL_PUE |	\
 		PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_MED |	\
 		PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
@@ -7225,6 +7229,8 @@ typedef enum iomux_config {
 
 #define  MX6Q_PAD_SD1_DAT1__USDHC1_DAT1		\
 		(_MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD1_DAT1__USDHC1_DAT1_50MHZ_40OHM		\
+		(_MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_50MHZ_40OHM))
 #define  MX6Q_PAD_SD1_DAT1__ECSPI5_SS0		\
 		(_MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_SD1_DAT1__PWM3_PWMO		\
@@ -7242,6 +7248,8 @@ typedef enum iomux_config {
 
 #define  MX6Q_PAD_SD1_DAT0__USDHC1_DAT0		\
 		(_MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD1_DAT0__USDHC1_DAT0_50MHZ_40OHM		\
+		(_MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_50MHZ_40OHM))
 #define  MX6Q_PAD_SD1_DAT0__ECSPI5_MISO		\
 		(_MX6Q_PAD_SD1_DAT0__ECSPI5_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_SD1_DAT0__CAAM_WRAPPER_RNG_OSC_OBS		\
@@ -7259,6 +7267,8 @@ typedef enum iomux_config {
 
 #define  MX6Q_PAD_SD1_DAT3__USDHC1_DAT3		\
 		(_MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD1_DAT3__USDHC1_DAT3_50MHZ_40OHM		\
+		(_MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_50MHZ_40OHM))
 #define  MX6Q_PAD_SD1_DAT3__ECSPI5_SS2		\
 		(_MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_SD1_DAT3__GPT_CMPOUT3		\
@@ -7276,6 +7286,8 @@ typedef enum iomux_config {
 
 #define  MX6Q_PAD_SD1_CMD__USDHC1_CMD		\
 		(_MX6Q_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD1_CMD__USDHC1_CMD_50MHZ_40OHM		\
+		(_MX6Q_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_50MHZ_40OHM))
 #define  MX6Q_PAD_SD1_CMD__ECSPI5_MOSI		\
 		(_MX6Q_PAD_SD1_CMD__ECSPI5_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_SD1_CMD__PWM4_PWMO		\
@@ -7289,6 +7301,8 @@ typedef enum iomux_config {
 
 #define  MX6Q_PAD_SD1_DAT2__USDHC1_DAT2		\
 		(_MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD1_DAT2__USDHC1_DAT2_50MHZ_40OHM		\
+		(_MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_50MHZ_40OHM))
 #define  MX6Q_PAD_SD1_DAT2__ECSPI5_SS1		\
 		(_MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_SD1_DAT2__GPT_CMPOUT2		\
@@ -7306,6 +7320,8 @@ typedef enum iomux_config {
 
 #define  MX6Q_PAD_SD1_CLK__USDHC1_CLK		\
 		(_MX6Q_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL))
+#define  MX6Q_PAD_SD1_CLK__USDHC1_CLK_50MHZ_40OHM		\
+		(_MX6Q_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(MX6Q_USDHC_PAD_CTRL_50MHZ_40OHM))
 #define  MX6Q_PAD_SD1_CLK__ECSPI5_SCLK		\
 		(_MX6Q_PAD_SD1_CLK__ECSPI5_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
 #define  MX6Q_PAD_SD1_CLK__OSC32K_32K_OUT		\