diff options
| author | Danny Nold <dannynold@freescale.com> | 2010-07-30 13:00:25 -0500 |
|---|---|---|
| committer | Alan Tull <r80115@freescale.com> | 2010-09-25 09:49:45 -0500 |
| commit | 4ed61d89ec30d31887eb7b31ad89f757c9ea337e (patch) | |
| tree | a1d8c9765bf151e2d7e0663103eadb570310b7a4 | |
| parent | a8ae0d6193cad4f58f204f50b6dad6610db067b5 (diff) | |
ENGR00125782 - EPDC AXI clk should be disabled before exiting clk init
Leaving EPDC AXI enabled is bad for power management. EPDC/Display
clks must be enabled before clock rate can be set. We must then disable
these clocks before completing init.
Signed-off-by: Danny Nold <dannynold@freescale.com>
| -rw-r--r-- | arch/arm/mach-mx5/clock_mx50.c | 24 |
1 files changed, 17 insertions, 7 deletions
diff --git a/arch/arm/mach-mx5/clock_mx50.c b/arch/arm/mach-mx5/clock_mx50.c index d576e73b3232..39b7e5901cb3 100644 --- a/arch/arm/mach-mx5/clock_mx50.c +++ b/arch/arm/mach-mx5/clock_mx50.c @@ -2410,10 +2410,8 @@ static int _clk_display_axi_set_rate(struct clk *clk, unsigned long rate) reg |= new_div << MXC_CCM_DISPLAY_AXI_DIV_OFFSET; __raw_writel(reg, MXC_CCM_DISPLAY_AXI); -#if 0 while (__raw_readl(MXC_CCM_CSR2) & MXC_CCM_CSR2_DISPLAY_AXI_BUSY) ; -#endif return 0; } @@ -2428,6 +2426,7 @@ static struct clk display_axi_clk = { .disable = _clk_disable, .enable_reg = MXC_CCM_DISPLAY_AXI, .enable_shift = MXC_CCM_DISPLAY_AXI_CLKGATE_OFFSET, + .flags = RATE_PROPAGATES, }; /* TODO: check Auto-Slow Mode */ @@ -2609,7 +2608,8 @@ static void _clk_epdc_axi_disable(struct clk *clk) /* TODO: check Auto-Slow Mode */ static struct clk epdc_axi_clk = { - .parent = &apbh_dma_clk, + .parent = &osc_clk, + .secondary = &apbh_dma_clk, .set_parent = _clk_epdc_axi_set_parent, .get_rate = _clk_epdc_axi_get_rate, .set_rate = _clk_epdc_axi_set_rate, @@ -3052,15 +3052,25 @@ int __init mx50_clocks_init(unsigned long ckil, unsigned long osc, unsigned long clk_set_parent(&cspi_main_clk, &lp_apm_clk); clk_set_rate(&cspi_main_clk, 12000000); - /* set DISPLAY_AXI to 200Mhz */ + /* + * Set DISPLAY_AXI to 200Mhz + * For Display AXI, source clocks must be + * enabled before dividers can be changed + */ clk_set_parent(&display_axi_clk, &pfd2_clk); + clk_enable(&display_axi_clk); clk_set_rate(&display_axi_clk, 200000000); + clk_disable(&display_axi_clk); - /* Enable and set EPDC AXI to 200MHz - TO DO + /* + * Enable and set EPDC AXI to 200MHz + * For EPDC AXI, source clocks must be + * enabled before dividers can be changed + */ clk_set_parent(&epdc_axi_clk, &pfd3_clk); clk_enable(&epdc_axi_clk); - clk_set_rate(&epdc_axi_clk, 200000000);*/ + clk_set_rate(&epdc_axi_clk, 200000000); + clk_disable(&epdc_axi_clk); clk_set_parent(&epdc_pix_clk, &pfd5_clk); |