diff options
| author | Li Jun <b47624@freescale.com> | 2015-01-20 16:03:35 +0800 |
|---|---|---|
| committer | Peter Chen <peter.chen@freescale.com> | 2015-01-26 13:18:05 +0800 |
| commit | a079cf466ff3772adee0cc902b7d7b3a60d7a8bc (patch) | |
| tree | d46d339ad095e9cbc355ef936d11e7ca31c6b253 | |
| parent | 9b209436ec923eca8e91510d9bca332a50360328 (diff) | |
MLK-10086-1 usb: doc: ci-hdrc-imx: update for hsic controller
Update for HSIC controller
Signed-off-by: Peter Chen <peter.chen@freescale.com>
| -rw-r--r-- | Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt b/Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt index 4ac8e27568fd..ce547ff9e279 100644 --- a/Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt +++ b/Documentation/devicetree/bindings/usb/ci-hdrc-imx.txt @@ -24,6 +24,12 @@ Optional properties: please do not set it. - fsl,anatop: phandle for anatop module, anatop module is only existed at imx6 SoC series. +- pinctrl-names: for names of hsic pin group +- pinctrl-0: hsic "idle" pin group +- pinctrl-1: hsic "active" pin group +- osc-clkgate-delay: the delay between powering up the xtal 24MHz clock + and release the clock to the digital logic inside the analog block, + 0 <= osc-clkgate-delay <= 7. - maximum-speed: limit the maximum connection speed to "full-speed". - tpl-support: TPL (Targeted Peripheral List) feature for targeted hosts @@ -38,6 +44,10 @@ usb@02184000 { /* USB OTG */ external-vbus-divider; imx6-usb-charger-detection; fsl,anatop = <&anatop>; + pinctrl-names = "idle", "active"; + pinctrl-0 = <&pinctrl_usbh2_1>; + pinctrl-1 = <&pinctrl_usbh2_2>; + osc-clkgate-delay = <0x3>; maximum-speed = "full-speed"; tpl-support; }; |