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authorAlban Bedel <alban.bedel@avionic-design.de>2013-08-11 19:59:19 +0200
committerVinod Koul <vinod.koul@intel.com>2013-09-02 11:49:56 +0530
commitf3287a5206cae1244601d50a4d2a9a96a521c1ee (patch)
treeb963749b7277eaaa080c4b201adb8a7343421ec7
parent5110e51d127221c93f331841e601612b187b60f4 (diff)
dmaengine: PL08x: Fix reading the byte count in cctl
There are more fields than just SWIDTH in CH_CONTROL register, so read register value must be masked in addition to shifting. Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
-rw-r--r--drivers/dma/amba-pl08x.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index 4e4c3df7f151..6b9cba2fd7f1 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -480,6 +480,8 @@ static inline u32 get_bytes_in_cctl(u32 cctl)
/* The source width defines the number of bytes */
u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK;
+ cctl &= PL080_CONTROL_SWIDTH_MASK;
+
switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
case PL080_WIDTH_8BIT:
break;
@@ -498,6 +500,8 @@ static inline u32 get_bytes_in_cctl_pl080s(u32 cctl, u32 cctl1)
/* The source width defines the number of bytes */
u32 bytes = cctl1 & PL080S_CONTROL_TRANSFER_SIZE_MASK;
+ cctl &= PL080_CONTROL_SWIDTH_MASK;
+
switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
case PL080_WIDTH_8BIT:
break;