diff options
author | Prashant Gaikwad <pgaikwad@nvidia.com> | 2012-09-04 14:20:53 +0530 |
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committer | Riham Haidar <rhaidar@nvidia.com> | 2013-04-01 12:20:53 -0700 |
commit | 3c03afecf07d7b111b83500f865c56a152e83093 (patch) | |
tree | 11f0648be5c4317366cdd61d495171d67c36f658 | |
parent | 7663eeed750d98c5335e53d707af57fd1df81f83 (diff) |
arm: tegra: Define DT bindings for T114 EMC tables
Bug 999688
Bug 1243373
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Amit Kamath <akamath@nvidia.com>
Reviewed-on: http://git-master/r/130701
(cherry picked from commit 52d06b4f8288a05561840cb451e65d1cd386ad16)
Change-Id: I33b56bda4ac3c09442f142ce13e05a81497902d6
Signed-off-by: Jinyoung Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/212579
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
-rw-r--r-- | Documentation/devicetree/bindings/arm/tegra/emc.txt | 93 |
1 files changed, 93 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/tegra/emc.txt b/Documentation/devicetree/bindings/arm/tegra/emc.txt index f735e34932f7..5f4d00c188b0 100644 --- a/Documentation/devicetree/bindings/arm/tegra/emc.txt +++ b/Documentation/devicetree/bindings/arm/tegra/emc.txt @@ -172,3 +172,96 @@ optional properties: nvidia,emc-dsr = <0>; nvidia,emc-min-mv = <0>; }; + +Tables for Tegra114: + +Properties: +- name : Should be emc-table +- compatible : Should contain "nvidia,tegra11-emc-table". +- reg : either an opaque enumerator to tell different tables apart, or + the valid frequency for which the table should be used (in kHz). +- nvidia,revision : SDRAM revision. +- clock-frequency : the clock frequency for the EMC at which this + table should be used (in kHz). +- nvidia,emc-min-mv : Minimum voltage +- nvidia,source : Source name. +- nvidia,src-sel-reg : Source register settings +- nvidia, burst-regs-num : Number of emc-registers +- nvidia,emc-registers : a word array of EMC registers to be programmed + for operation at the 'clock-frequency' setting. + The order and contents of the registers are: + RC, RFC, RFC_SLR, RAS, RP, R2W, W2R, R2P, W2P, RD_RCD, WR_RCD, + RRD, REXT, WEXT, WDV, WDV_MASK, IBDLY, PUTERM_EXTRA, CDB_CNTL_2, + QRST, RDV_MASK, REFRESH, BURST_REFRESH_NUM, PRE_REFRESH_REQ_CNT, + PDEX2WR, PDEX2RD, PCHG2PDEN, ACT2PDEN, AR2PDEN, RW2PDEN, TXSR, + TXSRDLL, TCKE, TCKESR, TPD, TFAW, TRPAB, TCLKSTABLE, TCLKSTOP, + TREFBW, QUSE_EXTRA, ODT_WRITE, ODT_READ, FBIO_CFG5, CFG_DIG_DLL, + CFG_DIG_DLL_PERIOD, DLL_XFORM_DQS4, DLL_XFORM_DQS5, DLL_XFORM_DQS6, + DLL_XFORM_DQS7, DLL_XFORM_QUSE4, DLL_XFORM_QUSE5, DLL_XFORM_QUSE6, + DLL_XFORM_QUSE7, DLI_TRIM_TXDQS4, DLI_TRIM_TXDQS5, DLI_TRIM_TXDQS6, + DLI_TRIM_TXDQS7, XM2CMDPADCTRL, XM2CMDPADCTRL4, XM2DQSPADCTRL2, + XM2DQPADCTRL2, XM2CLKPADCTRL, XM2COMPPADCTRL, XM2VTTGENPADCTRL, + XM2VTTGENPADCTRL2, DSR_VTTGEN_DRV, TXDSRVTTGEN, FBIO_SPARE, + CTT_TERM_CTRL, ZCAL_INTERVAL, ZCAL_WAIT_CNT, MRS_WAIT_CNT, + MRS_WAIT_CNT2, AUTO_CAL_CONFIG2, AUTO_CAL_CONFIG3, CTT, + CTT_DURATION, DYN_SELF_REF_CONTROL, CA_TRAINING_TIMING_CNTL1, + CA_TRAINING_TIMING_CNTL2, EMEM_ARB_CFG, EMEM_ARB_OUTSTANDING_REQ, + EMEM_ARB_TIMING_RCD, EMEM_ARB_TIMING_RP, EMEM_ARB_TIMING_RC, + EMEM_ARB_TIMING_RAS, EMEM_ARB_TIMING_FAW, EMEM_ARB_TIMING_RRD, + EMEM_ARB_TIMING_RAP2PRE, EMEM_ARB_TIMING_WAP2PRE, EMEM_ARB_TIMING_R2R, + EMEM_ARB_TIMING_W2W, EMEM_ARB_TIMING_R2W, EMEM_ARB_TIMING_W2R, + EMEM_ARB_DA_TURNS, EMEM_ARB_DA_COVERS, EMEM_ARB_MISC0, + EMEM_ARB_RING1_THROTTLE +- nvidia, emc-trimmers-num : number of trimmer registers +- nvidia, emc-trimmer-0 : a word array of trimmer channel 0 settings +- nvidia, emc-trimmer-1 : a word array of trimmer channel 1 settings + The order and contents of the registers are: + CDB_CNTL_1, FBIO_CFG6, QUSE, INPUT, EINPUT_DURATION, DLL_XFORM_DQS0, + QSAFE, DLL_XFORM_QUSE0, RDV, XM2DQSPADCTRL4, XM2DQSPADCTRL3, DLL_XFORM_DQ0 + AUTO_CAL_CONFIG, DLL_XFORM_ADDR0, XM2CLKPADCTRL2, DLI_TRIM_TXDQS0, + DLL_XFORM_ADDR1, DLL_XFORM_ADDR2, DLL_XFORM_DQS1, DLL_XFORM_DQS2, + DLL_XFORM_DQS3, DLL_XFORM_DQ1, DLL_XFORM_DQ2, DLL_XFORM_DQ3, + DLI_TRIM_TXDQS1, DLI_TRIM_TXDQS2, DLI_TRIM_TXDQS3, DLL_XFORM_QUSE1, + DLL_XFORM_QUSE2, DLL_XFORM_QUSE3 + +- nvidia, burst-up-down-regs-num : Number of burst up/down registers +- nvidia, burst-up-down-regs : a word array of burst register values + The order and contents of the registers are: + PTSA_GRANT_DECREMENT, LATENCY_ALLOWANCE_G2_0, LATENCY_ALLOWANCE_G2_1, + LATENCY_ALLOWANCE_NV_0, LATENCY_ALLOWANCE_NV2_0, LATENCY_ALLOWANCE_NV_2, + LATENCY_ALLOWANCE_NV_1, LATENCY_ALLOWANCE_NV2_1, LATENCY_ALLOWANCE_NV3, + LATENCY_ALLOWANCE_EPP_0, LATENCY_ALLOWANCE_EPP_1 + +- nvidia,emc-zcal-cnt-long : EMC_ZCAL_WAIT_CNT after clock change +- nvidia,emc-acal-interval : EMC_AUTO_CAL_INTERVAL +- nvidia,emc-mode-cfg : Mode config register +- nvidia,emc-mode-reset : Mode Register 0 +- nvidia,emc-mode-1 : Mode Register 1 +- nvidia,emc-mode-2 : Mode Register 2 +- nvidia,emc-mode-4 : Mode Register 4 + +optional properties: +- nvidia,emc-clock-latency-change : latency information + + emc-table@166000 { + reg = <166000>; + compatible = "nvidia,tegra11-emc-table"; + clock-frequency = < 166000 >; + nvidia,revision = <0>; + nvidia,source = "pll_m"; + nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 0 0 0 0 0 0 0 0 0 0 0 0>; + nvidia,emc-zcal-cnt-long = <0>; + nvidia,emc-acal-interval = <0>; + nvidia,emc-mode-reset = <0>; + nvidia,emc-mode-1 = <0>; + nvidia,emc-mode-2 = <0>; + nvidia,emc-mode-4 = <0>; + nvidia,emc-min-mv = <0>; + }; |