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authorLaxman Dewangan <ldewangan@nvidia.com>2011-07-15 14:36:16 +0530
committerVarun Colbert <vcolbert@nvidia.com>2011-07-18 17:42:44 -0700
commitbbbb88d21d166eeb4de4d83af073f08bdcbe1257 (patch)
tree55848673afb311114291095c74a97ee3664c092d
parent3f524b73df7fe3860ae532692b55e40274ddc043 (diff)
arm: tegra: cardhu: Set AVDD_PLL and AVDD_PLL_SATA to proper voltage
Setting the rail voltage of the AVDD_PLLs to 1.2V and rail voltage of PLL_SATA to 1.05V. Change-Id: Ibf5bb1d11b7b15cabb68f90da7e24dd999915c55 Reviewed-on: http://git-master/r/41179 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
-rw-r--r--arch/arm/mach-tegra/board-cardhu-power.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/board-cardhu-power.c b/arch/arm/mach-tegra/board-cardhu-power.c
index 4ab54218d416..257f7f4ae2f4 100644
--- a/arch/arm/mach-tegra/board-cardhu-power.c
+++ b/arch/arm/mach-tegra/board-cardhu-power.c
@@ -180,7 +180,7 @@ TPS_PDATA_INIT(vddctrl, 0, 600, 1400, 0, 1, 1, 0, -1, 0, 0, EXT_CTRL_EN1);
TPS_PDATA_INIT(vio, 0, 1500, 3300, 0, 1, 1, 0, -1, 0, 0, 0);
TPS_PDATA_INIT(ldo1, 0, 1000, 3300, tps6591x_rails(VDD_2), 0, 0, 0, -1, 0, 1, 0);
-TPS_PDATA_INIT(ldo2, 0, 1000, 3300, tps6591x_rails(VDD_2), 0, 0, 0, -1, 0, 1, 0);
+TPS_PDATA_INIT(ldo2, 0, 1050, 1050, tps6591x_rails(VDD_2), 0, 0, 1, -1, 0, 1, 0);
TPS_PDATA_INIT(ldo3, e118x, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0);
TPS_PDATA_INIT(ldo3, e1198, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0);
@@ -189,7 +189,7 @@ TPS_PDATA_INIT(ldo5, e118x, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0);
TPS_PDATA_INIT(ldo5, e1198, 1000, 3300, 0, 0, 0, 0, -1, 0, 0, 0);
TPS_PDATA_INIT(ldo6, 0, 1000, 3300, tps6591x_rails(VIO), 0, 0, 0, -1, 0, 0, 0);
-TPS_PDATA_INIT(ldo7, 0, 1000, 3300, tps6591x_rails(VIO), 1, 0, 0, -1, 0, 0, 0);
+TPS_PDATA_INIT(ldo7, 0, 1200, 1200, tps6591x_rails(VIO), 1, 1, 1, -1, 0, 0, 0);
TPS_PDATA_INIT(ldo8, 0, 1000, 3300, tps6591x_rails(VIO), 1, 0, 0, -1, 0, 0, 0);
#if defined(CONFIG_RTC_DRV_TPS6591x)