diff options
| author | Venkata(Muni) Anda <vanda@nvidia.com> | 2010-04-19 22:28:26 -0700 |
|---|---|---|
| committer | Gary King <gking@nvidia.com> | 2010-04-20 16:44:44 -0700 |
| commit | 1301961bc05d94b47e7a0c287c351a16aef6bc20 (patch) | |
| tree | b38585611cf8ab3ab4e4e25ea583320bdf4461d9 | |
| parent | 442a19224eeae74164e35fe67e91b401fd202dea (diff) | |
tegra power: Enable CPU standby line during initialization.
CPU power request line needs to be explicitly enabled so that PMUs with
separate request lines for CPU and core rails will shutdown the CPU power
rail as expected.
Change-Id: I95bc048b6e1df9029e900d33c4c0f5aa63c008a7
Reviewed-on: http://git-master/r/1156
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Venkata (Muni) Anda <vanda@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/power-t2.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/power-t2.c b/arch/arm/mach-tegra/power-t2.c index 44b47879f4a0..ae302a7b529d 100644 --- a/arch/arm/mach-tegra/power-t2.c +++ b/arch/arm/mach-tegra/power-t2.c @@ -279,7 +279,7 @@ void power_lp0_init(void) //Enable CPU power request. Leave it enabled to be ready for LP2/LP1. Reg = NV_PMC_REGR(g_pPMC, CNTRL); Reg = NV_FLD_SET_DRF_DEF(APBDEV_PMC, CNTRL, CPUPWRREQ_OE, ENABLE, Reg); - NV_ASSERT(Reg == APBDEV_PMC_CNTRL_0_CPUPWRREQ_OE_ENABLE); + NV_PMC_REGW(g_pPMC,CNTRL,Reg); //If the system supports deep sleep (LP0), initialize PMC accordingly. if (LPStateInfo->LowestPowerState == NvOdmSocPowerState_DeepSleep) |