diff options
| author | Alex Frid <afrid@nvidia.com> | 2010-01-11 11:20:47 -0800 |
|---|---|---|
| committer | Alex Frid <afrid@nvidia.com> | 2010-01-11 16:56:34 -0800 |
| commit | e9ef83b5d6f7a8c367a3ff2a88f373c3bb9312c1 (patch) | |
| tree | 7ddf09e12c7ef96599633c27cd6ac25fe55125cc | |
| parent | 9295e7abc68aea6b3ecd8191fa01e4661f281481 (diff) | |
tegra RM: Init/restore DDR PD state machine.
Made sure DDR PD state machine is enabled during EMC DFS initialization
/restoration from LP0 before the 1st EMC clock change is triggered.
Change-Id: I26e16e30065cc356d70eb06ca51f4adeda728612
| -rw-r--r-- | arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_clock_config.c | 22 |
1 files changed, 21 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_clock_config.c b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_clock_config.c index 8ee8277f1204..882d0c184c68 100644 --- a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_clock_config.c +++ b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_clock_config.c @@ -45,6 +45,9 @@ // Enable CPU/EMC ratio policy #define NVRM_LIMIT_CPU_EMC_RATIO (1) +// Use DRAM power down mode with EMC clock change +#define NVRM_EMC_CLKCHANGE_PD (1) + // Default CPU power good delay #define NVRM_DEFAULT_CPU_PWRGOOD_US (2000) @@ -238,6 +241,9 @@ static NvBool Ap20EmcClkChangeConfig( NvRmDeviceHandle hRmDevice) { +// NO-DEVICE for dummy MRW/MRS commands +#define NULL_DEV_SELECTN (3) + NvU32 cfg2, cfg5; cfg2 = NV_REGR(hRmDevice, NvRmPrivModuleID_ExternalMemoryController, 0, @@ -247,14 +253,28 @@ Ap20EmcClkChangeConfig( switch (NV_DRF_VAL(EMC, FBIO_CFG5, DRAM_TYPE, cfg5)) { - case EMC_FBIO_CFG5_0_DRAM_TYPE_DDR1: case EMC_FBIO_CFG5_0_DRAM_TYPE_LPDDR2: +#if NVRM_EMC_CLKCHANGE_PD + // Dummy mode control command to activate PD state machine + NV_REGW(hRmDevice, + NvRmPrivModuleID_ExternalMemoryController, 0, EMC_MRW_0, + NV_DRF_NUM(EMC, MRW, MRW_DEV_SELECTN, NULL_DEV_SELECTN)); + NvOsWaitUS(NVRM_CLOCK_CHANGE_DELAY); + cfg2 = NV_FLD_SET_DRF_DEF( EMC, CFG_2, CLKCHANGE_PD_ENABLE, ENABLED, cfg2); cfg2 = NV_FLD_SET_DRF_DEF( EMC, CFG_2, CLKCHANGE_SR_ENABLE, DISABLED, cfg2); break; +#endif case EMC_FBIO_CFG5_0_DRAM_TYPE_DDR2: +#if NVRM_EMC_CLKCHANGE_PD + // Dummy mode control command to activate PD state machine + NV_REGW(hRmDevice, + NvRmPrivModuleID_ExternalMemoryController, 0, EMC_MRS_0, + NV_DRF_NUM(EMC, MRS, MRS_DEV_SELECTN, NULL_DEV_SELECTN)); + NvOsWaitUS(NVRM_CLOCK_CHANGE_DELAY); +#endif cfg2 = NV_FLD_SET_DRF_DEF( EMC, CFG_2, CLKCHANGE_PD_ENABLE, DISABLED, cfg2); cfg2 = NV_FLD_SET_DRF_DEF( |