Merge change I5f44277d into android-tegra-2.6.29

* changes:
  tegra RM: adjusted DVFS thresholds.

6 files changed, 48 insertions, 28 deletions

diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_power.c b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_power.c
index caebecd1c0bc..e7781256b71e 100644
--- a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_power.c
+++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_power.c
@@ -531,33 +531,35 @@ void NvRmPrivCoreVoltageInit(NvRmDeviceHandle hRmDevice)
         NV_ASSERT(!"Unexpected initial RTC voltage");
         return;
     }
-    NvRmPmuSetVoltage(hRmDevice, RtcRailAddress, NominalCoreMv, NULL);
-    NvRmPmuSetVoltage(hRmDevice, CoreRailAddress, NominalCoreMv, NULL);
+    // If core voltage is going up, update it before CPU
+    if (CurrentCoreMv <= NominalCoreMv)
+    {
+        NvRmPmuSetVoltage(hRmDevice, RtcRailAddress, NominalCoreMv, NULL);
+        NvRmPmuSetVoltage(hRmDevice, CoreRailAddress, NominalCoreMv, NULL);
+    }
 
     // If the platform has dedicated CPU voltage rail, make sure it is set to
-    // nominal level first. Similar to the core, CPU boot voltage is expected
-    // to be within one safe step from nominal.
+    // nominal level as well (bump PMU ref count along the way).
     if (NvRmPrivIsCpuRailDedicated(hRmDevice))
     {
-        NvRmMilliVolts CurrentCpuMv = 0;
         NvRmMilliVolts NominalCpuMv = NvRmPrivModuleVscaleGetMV(
-            hRmDevice, NvRmModuleID_Cpu, NvRmFreqMaximum);
+            hRmDevice, NvRmModuleID_Cpu,
+            NvRmPrivGetSocClockLimits(NvRmModuleID_Cpu)->MaxKHz);
 
         pPmuRail = NvOdmPeripheralGetGuid(NV_VDD_CPU_ODM_ID);
         NV_ASSERT(pPmuRail);
         NV_ASSERT(pPmuRail->NumAddress);
         CpuRailAddress = pPmuRail->AddressList[0].Address;
-
-        NvRmPmuGetVoltage(hRmDevice, CpuRailAddress, &CurrentCpuMv);
-        if((CurrentCpuMv > (NominalCpuMv + NVRM_SAFE_VOLTAGE_STEP_MV)) ||
-           ((CurrentCpuMv + NVRM_SAFE_VOLTAGE_STEP_MV) < NominalCpuMv))
-        {
-            NV_ASSERT(!"Unexpected initial CPU voltage");
-            return;
-        }
         NvRmPmuSetVoltage(hRmDevice, CpuRailAddress, NominalCpuMv, NULL);
     }
 
+    // If core voltage is going down, update it after CPU voltage
+    if (CurrentCoreMv > NominalCoreMv)
+    {
+        NvRmPmuSetVoltage(hRmDevice, RtcRailAddress, NominalCoreMv, NULL);
+        NvRmPmuSetVoltage(hRmDevice, CoreRailAddress, NominalCoreMv, NULL);
+    }
+
     // Always On System I/O, DDR IO and RX DDR (if exist) - set nominal,
     // bump ref count
     NvRmPrivPmuRailControl(hRmDevice, NV_VDD_SYS_ODM_ID, NV_TRUE);
diff --git a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_clock_config.c b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_clock_config.c
index 4add3ff74fa9..8b57925ce6c6 100644
--- a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_clock_config.c
+++ b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_clock_config.c
@@ -55,7 +55,7 @@
 #define NVRM_DEFAULT_PMU_ACCURACY_PCT (3)
 
 // Minimum core over CPU voltage margin (at SoC)
-#define NV_AP20_CORE_OVER_CPU_MV (100)
+#define NV_AP20_CORE_OVER_CPU_MV (120)
 
 /*****************************************************************************/
 
diff --git a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.c b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.c
index 8bc72a4c2928..f1fadbdbc201 100644
--- a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.c
+++ b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.c
@@ -223,7 +223,8 @@ NvRmPrivAp20DttPolicyUpdate(
                 break;
         }
         NV_ASSERT(steps);
-        s_CpuThrottleMaxKHz = p[steps-1];
+        s_CpuThrottleMaxKHz = NV_MIN(
+            NvRmPrivGetSocClockLimits(NvRmModuleID_Cpu)->MaxKHz, p[steps-1]);
         s_CpuThrottleMinKHz =
             NvRmPrivGetSocClockLimits(NvRmModuleID_Cpu)->MaxKHz / 2;
         NV_ASSERT(s_CpuThrottleMaxKHz > s_CpuThrottleMinKHz); 
@@ -364,19 +365,17 @@ NvRmPrivAp20GetPmRequest(
 
     // Slave CPU1 power management policy thresholds:
     // - use fixed values if they are defined explicitly, otherwise
-    // - use max CPU frequency at min CPU voltage) as CPU1 OffMax threshold,
+    // - set CPU1 OffMax threshold at 2/3 of cpu frequency range,
     //   and half of that frequency as CPU1 OnMin threshold
     if ((s_Cpu1OffMaxKHz == 0) && (s_Cpu1OnMinKHz == 0))
     {
-        NvU32 n;
-        const NvRmFreqKHz* p = NvRmPrivModuleVscaleGetMaxKHzList(
-            hRmDevice, NvRmModuleID_Cpu, &n);
+        NvRmFreqKHz MaxKHz =
+            NvRmPrivGetSocClockLimits(NvRmModuleID_Cpu)->MaxKHz;
 
-        NV_ASSERT (p && n);
         s_Cpu1OnMinKHz = NVRM_CPU1_ON_MIN_KHZ ?
-                         NVRM_CPU1_ON_MIN_KHZ : (p[0] >> 1);
+                         NVRM_CPU1_ON_MIN_KHZ : (MaxKHz / 3);
         s_Cpu1OffMaxKHz = NVRM_CPU1_OFF_MAX_KHZ ?
-                          NVRM_CPU1_OFF_MAX_KHZ : p[0];
+                          NVRM_CPU1_OFF_MAX_KHZ : (2 * MaxKHz / 3);
         NV_ASSERT(s_Cpu1OnMinKHz < s_Cpu1OffMaxKHz);
     }
 
diff --git a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.h b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.h
index 33f505ff86f8..5a6e13848715 100644
--- a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.h
+++ b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.h
@@ -225,7 +225,7 @@ extern "C"
 
 /// Default low corners for core and dedicated CPU voltages
 #define NVRM_AP20_LOW_CORE_MV (1200)
-#define NVRM_AP20_LOW_CPU_MV (850)
+#define NVRM_AP20_LOW_CPU_MV (750)
 
 /*****************************************************************************/
 
diff --git a/arch/arm/mach-tegra/nvrm/core/common/nvrm_power_dfs.c b/arch/arm/mach-tegra/nvrm/core/common/nvrm_power_dfs.c
index bc4ebf099024..7cd0abeb9ce6 100644
--- a/arch/arm/mach-tegra/nvrm/core/common/nvrm_power_dfs.c
+++ b/arch/arm/mach-tegra/nvrm/core/common/nvrm_power_dfs.c
@@ -78,6 +78,9 @@
 #define NVRM_DTT_USE_INTERRUPT (1)
 #define NVRM_DTT_RANGE_CHANGE_PRINTF (1)
 
+// Allow PMUs with CPU voltage range above chip minimum
+#define NVRM_DVS_ACCEPT_PMU_HIGH_CPU_MIN (1)
+
 /*****************************************************************************/
 
 // TODO: Always Disable before check-in
@@ -2278,10 +2281,11 @@ void NvRmPrivDvsInit(void)
             NvOdmPeripheralGetGuid(NV_VDD_CPU_ODM_ID);
 
         pDvs->NominalCpuMv = NvRmPrivModuleVscaleGetMV(
-            pDfs->hRm, NvRmModuleID_Cpu, NvRmFreqMaximum);
-        pDvs->MinCpuMv = NvRmPrivModuleVscaleGetMV(pDfs->hRm, NvRmModuleID_Cpu,
+            pDfs->hRm, NvRmModuleID_Cpu,
+            NvRmPrivGetSocClockLimits(NvRmModuleID_Cpu)->MaxKHz);
+        pDvs->MinCpuMv = NvRmPrivModuleVscaleGetMV(
+            pDfs->hRm, NvRmModuleID_Cpu,
             NvRmPrivGetSocClockLimits(NvRmModuleID_Cpu)->MinKHz);
-        pDvs->LowCornerCpuMv = pDvs->MinCpuMv;
 
         NV_ASSERT(pCpuRail && pCpuRail->NumAddress);
         pDvs->CpuRailAddress = pCpuRail->AddressList[0].Address;
@@ -2290,9 +2294,15 @@ void NvRmPrivDvsInit(void)
                   (cap.StepMilliVolts <= NVRM_SAFE_VOLTAGE_STEP_MV));
         NV_ASSERT((cap.StepMilliVolts) &&
                   (cap.StepMilliVolts <= NVRM_CORE_RESOLUTION_MV));
+#if NVRM_DVS_ACCEPT_PMU_HIGH_CPU_MIN
+        pDvs->MinCpuMv = NV_MAX(pDvs->MinCpuMv, cap.MinMilliVolts);
+        NV_ASSERT(pDvs->MinCpuMv <= pDvs->NominalCpuMv);
+#else
         NV_ASSERT(cap.MinMilliVolts <= pDvs->MinCpuMv);
+#endif
         NV_ASSERT(cap.MaxMilliVolts >= pDvs->NominalCpuMv);
         pDvs->CpuOTPMv = cap.requestMilliVolts;
+        pDvs->LowCornerCpuMv = pDvs->MinCpuMv;
 
         // CPU rail behaviour after CPU request signal On-Off-On transition
         if (NvOdmQueryGetPmuProperty(&PmuProperty))
@@ -2331,11 +2341,20 @@ void NvRmPrivDvsInit(void)
     pDvs->DvsCorner.ModulesMv = pDvs->NominalCoreMv;
 
     if ((pDfs->hRm->ChipId.Id == 0x15) || (pDfs->hRm->ChipId.Id == 0x16))
+    {
         pDvs->LowCornerCoreMv = NV_MAX(NVRM_AP15_LOW_CORE_MV, pDvs->MinCoreMv);
+        pDvs->LowCornerCoreMv =
+            NV_MIN(pDvs->LowCornerCoreMv, pDvs->NominalCoreMv);
+    }
     else if (pDfs->hRm->ChipId.Id == 0x20)
     {
         pDvs->LowCornerCoreMv = NV_MAX(NVRM_AP20_LOW_CORE_MV, pDvs->MinCoreMv);
+        pDvs->LowCornerCoreMv =
+            NV_MIN(pDvs->LowCornerCoreMv, pDvs->NominalCoreMv);
+
         pDvs->LowCornerCpuMv = NV_MAX(NVRM_AP20_LOW_CPU_MV, pDvs->MinCpuMv);
+        pDvs->LowCornerCpuMv =
+            NV_MIN(pDvs->LowCornerCpuMv, pDvs->NominalCpuMv);
     }
 }
 
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/ad5258_dpm.h b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/ad5258_dpm.h
index b22fa87a83e2..342376d33f81 100644
--- a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/ad5258_dpm.h
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/max8907b/ad5258_dpm.h
@@ -58,7 +58,7 @@ extern "C"
  * particular schematic combining constant resistors, DPM, and DCDC supply.
  */
 // On Whistler:
-#define AD5258_V0   (818)
+#define AD5258_V0   (815)
 #define AD5258_M1   (229)        
 #define AD5258_M2   (4571)
 #define AD5258_b    (10)