diff options
| author | Maxime Ripard <maxime.ripard@free-electrons.com> | 2013-07-16 16:45:38 +0200 |
|---|---|---|
| committer | Daniel Lezcano <daniel.lezcano@linaro.org> | 2013-07-18 15:27:21 +0200 |
| commit | 7e14183469d8aa2c7aa7675a6156e7846dda7748 (patch) | |
| tree | 2ce43e7591f668178440cb36c89e41227e68d5ce | |
| parent | a2c49e7b553a28f10ab34e5da538ed4a45a697a7 (diff) | |
clocksource: sun4i: Fix bug when switching from periodic to oneshot modes
The interval was firing at was set up at probe time, and only changed in
the set_next_event, and never changed back, which is not really what is
expected.
When enabling the periodic mode, now set an interval to tick every
jiffy.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
| -rw-r--r-- | drivers/clocksource/sun4i_timer.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/drivers/clocksource/sun4i_timer.c b/drivers/clocksource/sun4i_timer.c index 2fadb3ba59db..8ead0258740a 100644 --- a/drivers/clocksource/sun4i_timer.c +++ b/drivers/clocksource/sun4i_timer.c @@ -38,6 +38,7 @@ #define TIMER_CNTVAL_REG(val) (0x10 * (val) + 0x18) static void __iomem *timer_base; +static u32 ticks_per_jiffy; /* * When we disable a timer, we need to wait at least for 2 cycles of @@ -74,7 +75,8 @@ static void sun4i_clkevt_time_start(u8 timer, bool periodic) else val |= TIMER_CTL_ONESHOT; - writel(val | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(timer)); + writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD, + timer_base + TIMER_CTL_REG(timer)); } static void sun4i_clkevt_mode(enum clock_event_mode mode, @@ -83,6 +85,7 @@ static void sun4i_clkevt_mode(enum clock_event_mode mode, switch (mode) { case CLOCK_EVT_MODE_PERIODIC: sun4i_clkevt_time_stop(0); + sun4i_clkevt_time_setup(0, ticks_per_jiffy); sun4i_clkevt_time_start(0, true); break; case CLOCK_EVT_MODE_ONESHOT: @@ -169,9 +172,9 @@ static void __init sun4i_timer_init(struct device_node *node) clocksource_mmio_init(timer_base + TIMER_CNTVAL_REG(1), node->name, rate, 300, 32, clocksource_mmio_readl_down); - writel(rate / HZ, timer_base + TIMER_INTVAL_REG(0)); + ticks_per_jiffy = DIV_ROUND_UP(rate, HZ); - writel(TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M) | TIMER_CTL_RELOAD, + writel(TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M), timer_base + TIMER_CTL_REG(0)); ret = setup_irq(irq, &sun4i_timer_irq); |