diff options
author | Fabio Estevam <fabio.estevam@freescale.com> | 2013-09-02 23:51:41 -0300 |
---|---|---|
committer | Shawn Guo <shawn.guo@linaro.org> | 2013-09-26 13:01:33 +0800 |
commit | c9d96df207a2caadfb521c7b6108ef9172f5bf55 (patch) | |
tree | 8311bc08b5777699a9a66282a8cd0a5452401813 | |
parent | dc03a50f940db68250a3eadc6fc98bfe5a7d850a (diff) |
ARM: imx6qdl-wandboard: Add spdif support
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Nicolin Chen <b42378@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
-rw-r--r-- | arch/arm/boot/dts/imx6qdl-wandboard.dtsi | 13 | ||||
-rw-r--r-- | arch/arm/boot/dts/imx6qdl.dtsi | 21 |
2 files changed, 34 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi index b46208016b8d..df42d3ccb70e 100644 --- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi +++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi @@ -43,6 +43,13 @@ mux-int-port = <1>; mux-ext-port = <3>; }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif>; + spdif-out; + }; }; &audmux { @@ -93,6 +100,12 @@ status = "okay"; }; +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif_3>; + status = "okay"; +}; + &ssi1 { fsl,mode = "i2s-slave"; status = "okay"; diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index ccd55c2fdb67..2a3abf822378 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -136,8 +136,23 @@ ranges; spdif: spdif@02004000 { + compatible = "fsl,imx35-spdif"; reg = <0x02004000 0x4000>; interrupts = <0 52 0x04>; + dmas = <&sdma 14 18 0>, + <&sdma 15 18 0>; + dma-names = "rx", "tx"; + clocks = <&clks 197>, <&clks 3>, + <&clks 197>, <&clks 107>, + <&clks 0>, <&clks 118>, + <&clks 62>, <&clks 139>, + <&clks 0>; + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7"; + status = "disabled"; }; ecspi1: ecspi@02008000 { @@ -1010,6 +1025,12 @@ MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 >; }; + + pinctrl_spdif_3: spdifgrp-3 { + fsl,pins = < + MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0 + >; + }; }; uart1 { |