diff options
| author | Alex Frid <afrid@nvidia.com> | 2011-05-13 18:21:03 -0700 |
|---|---|---|
| committer | Varun Colbert <vcolbert@nvidia.com> | 2011-05-18 11:47:41 -0700 |
| commit | 327478a5336fac2abe792a01082b1d29810db2b0 (patch) | |
| tree | ad992c14e42a12494300ad3e7b3faa7bbf0b6aca | |
| parent | 48c4b1688bf22d263e691d11365e0078b6ddef97 (diff) | |
ARM: tegra: clock: Set Tegra3 CPU maximum rate to 1.3GHz
Set Tegra3 CPU maximum rate to 1.3MHz. Effective only on boards with
EDP table. Otherwise, the default EDP limit keeps rate below 1GHz.
Change-Id: I8221cf037cc957b45cafc7f59c76d3cf25816228
Reviewed-on: http://git-master/r/31617
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/tegra3_clocks.c | 24 |
1 files changed, 20 insertions, 4 deletions
diff --git a/arch/arm/mach-tegra/tegra3_clocks.c b/arch/arm/mach-tegra/tegra3_clocks.c index 25e05bee7264..213381078e65 100644 --- a/arch/arm/mach-tegra/tegra3_clocks.c +++ b/arch/arm/mach-tegra/tegra3_clocks.c @@ -3131,7 +3131,7 @@ static struct clk tegra_clk_cclk_g = { .inputs = mux_cclk_g, .reg = 0x368, .ops = &tegra_super_ops, - .max_rate = 1000000000, + .max_rate = 1300000000, }; static struct clk tegra_clk_cclk_lp = { @@ -3140,7 +3140,7 @@ static struct clk tegra_clk_cclk_lp = { .inputs = mux_cclk_lp, .reg = 0x370, .ops = &tegra_super_ops, - .max_rate = 1000000000, + .max_rate = 500000000, }; static struct clk tegra_clk_sclk = { @@ -3156,7 +3156,7 @@ static struct clk tegra_clk_virtual_cpu_g = { .name = "cpu_g", .parent = &tegra_clk_cclk_g, .ops = &tegra_cpu_ops, - .max_rate = 1000000000, + .max_rate = 1300000000, .u.cpu = { .main = &tegra_pll_x, .backup = &tegra_pll_p, @@ -3186,7 +3186,7 @@ static struct clk tegra_clk_cpu_cmplx = { .name = "cpu", .inputs = mux_cpu_cmplx, .ops = &tegra_cpu_cmplx_ops, - .max_rate = 1000000000, + .max_rate = 1300000000, }; static struct clk tegra_clk_cop = { @@ -3676,9 +3676,25 @@ static struct cpufreq_frequency_table freq_table_1p0GHz[] = { { 9, CPUFREQ_TABLE_END }, }; +static struct cpufreq_frequency_table freq_table_1p3GHz[] = { + { 0, 108000 }, + { 1, 216000 }, + { 2, 340000 }, + { 3, 480000 }, + { 4, 640000 }, + { 5, 760000 }, + { 6, 880000 }, + { 7, 1000000 }, + { 8, 1100000 }, + { 9, 1200000 }, + {10, 1300000 }, + {11, CPUFREQ_TABLE_END }, +}; + static struct tegra_cpufreq_table_data cpufreq_tables[] = { { freq_table_300MHz, 0, 1 }, { freq_table_1p0GHz, 2, 7 }, + { freq_table_1p3GHz, 2, 9, 1}, }; static void clip_cpu_rate_limits( |