diff options
author | Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com> | 2014-03-31 13:35:45 -0500 |
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committer | Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com> | 2014-04-01 15:49:42 -0500 |
commit | eecbe9a52587cf9eec30132fb9b8a6761f3a1e6d (patch) | |
tree | f0e2bea2d24caa3e704d1237d043cf32e110042c | |
parent | 82df785a4b38da969e306b2cd92abc40b9bbd056 (diff) |
ENGR00306309 ARM:imx:imx6qdl: Fix procedure to switch the parent of LDB_DI_CLK
Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk tree,
the glitchy parent mux of ldb_di[x]_clk can cause a glitch to enter the
ldb_di_ipu_div divider. If the divider gets locked up, no ldb_di[x]_clk is
generated, and the LVDS display will hang when the ipu_di_clk is sourced from
ldb_di_clk.
To fix the problem, both the new and current parent of the ldb_di_clk should
be disabled before the switch. This patch ensures that correct steps are
followed when ldb_di_clk parent is switched in the beginning of boot.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
-rw-r--r-- | arch/arm/mach-imx/clk-imx6q.c | 143 |
1 files changed, 133 insertions, 10 deletions
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c index 59ec5fe965fb..e09b1e8e78ac 100644 --- a/arch/arm/mach-imx/clk-imx6q.c +++ b/arch/arm/mach-imx/clk-imx6q.c @@ -74,6 +74,9 @@ static const char *cko_sels[] = { "cko1", "cko2", }; static const char *lvds_sels[] = { "arm", "pll1_sys", "dummy", "dummy", "dummy", "dummy", "dummy", "pll5_video_div", "dummy", "dummy", "pcie_ref", "sata_ref", "usbphy1", "usbphy2", }; static const char *pll_av_sels[] = { "osc", "lvds1_in", "lvds2_in", "dummy", }; +static void __iomem *anatop_base; +static void __iomem *ccm_base; + enum mx6q_clks { dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m, @@ -144,12 +147,120 @@ static struct clk_div_table video_div_table[] = { { } }; +static void init_ldb_clks(enum mx6q_clks new_parent) +{ + u32 reg; + + /* + * Need to follow a strict procedure when changing the LDB + * clock, else we can introduce a glitch. Things to keep in + * mind: + * 1. The current and new parent clocks must be disabled. + * 2. The default clock for ldb_dio_clk is mmdc_ch1 which has + * no CG bit. + * 3. In the RTL implementation of the LDB_DI_CLK_SEL mux + * the top four options are in one mux and the PLL3 option along + * with another option is in the second mux. There is third mux + * used to decide between the first and second mux. + * The code below switches the parent to the bottom mux first + * and then manipulates the top mux. This ensures that no glitch + * will enter the divider. + * + * Need to disable MMDC_CH1 clock manually as there is no CG bit + * for this clock. The only way to disable this clock is to move + * it topll3_sw_clk and then to disable pll3_sw_clk + * Make sure periph2_clk2_sel is set to pll3_sw_clk + */ + reg = readl_relaxed(ccm_base + 0x18); + reg &= ~(1 << 20); + writel_relaxed(reg, ccm_base + 0x18); + + /* + * Set MMDC_CH1 mask bit. + */ + reg = readl_relaxed(ccm_base + 0x4); + reg |= 1 << 16; + writel_relaxed(reg, ccm_base + 0x4); + + /* + * Set the periph2_clk_sel to the top mux so that + * mmdc_ch1 is from pll3_sw_clk. + */ + reg = readl_relaxed(ccm_base + 0x14); + reg |= 1 << 26; + writel_relaxed(reg, ccm_base + 0x14); + + /* + * Wait for the clock switch. + */ + while (readl_relaxed(ccm_base + 0x48)) + ; + + /* + * Disable pll3_sw_clk by selecting the bypass clock source. + */ + reg = readl_relaxed(ccm_base + 0xc); + reg |= 1 << 0; + writel_relaxed(reg, ccm_base + 0xc); + + /* + * Set the ldb_di0_clk and ldb_di1_clk to 111b. + */ + reg = readl_relaxed(ccm_base + 0x2c); + reg |= ((7 << 9) | (7 << 12)); + writel_relaxed(reg, ccm_base + 0x2c); + + /* + * Set the ldb_di0_clk and ldb_di1_clk to 100b. + */ + reg = readl_relaxed(ccm_base + 0x2c); + reg &= ~((7 << 9) | (7 << 12)); + reg |= ((4 << 9) | (4 << 12)); + writel_relaxed(reg, ccm_base + 0x2c); + + /* + * Perform the LDB parent clock switch. + */ + clk_set_parent(clk[ldb_di0_sel], clk[new_parent]); + clk_set_parent(clk[ldb_di1_sel], clk[new_parent]); + + /* + * Unbypass pll3_sw_clk. + */ + reg = readl_relaxed(ccm_base + 0xc); + reg &= ~(1 << 0); + writel_relaxed(reg, ccm_base + 0xc); + + /* + * Set the periph2_clk_sel back to the bottom mux so that + * mmdc_ch1 is from its original parent. + */ + reg = readl_relaxed(ccm_base + 0x14); + reg &= ~(1 << 26); + writel_relaxed(reg, ccm_base + 0x14); + + /* + * Wait for the clock switch. + */ + while (readl_relaxed(ccm_base + 0x48)) + ; + + /* + * Clear MMDC_CH1 mask bit. + */ + reg = readl_relaxed(ccm_base + 0x4); + reg &= ~(1 << 16); + writel_relaxed(reg, ccm_base + 0x4); + +} + static void __init imx6q_clocks_init(struct device_node *ccm_node) { struct device_node *np; void __iomem *base; int i, irq; int ret; + u32 reg; clk[dummy] = imx_clk_fixed("dummy", 0); clk[ckil] = imx_obtain_fixed_clock("ckil", 0); @@ -160,7 +271,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[anaclk2] = imx_obtain_fixed_clock("anaclk2", 0); np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); - base = of_iomap(np, 0); + anatop_base = base = of_iomap(np, 0); WARN_ON(!base); /* Audio/video PLL post dividers do not work on i.MX6q revision 1.0 */ @@ -240,7 +351,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk[pll5_video_div] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); np = ccm_node; - base = of_iomap(np, 0); + ccm_base = base = of_iomap(np, 0); WARN_ON(!base); imx6_pm_set_ccm_base(base); @@ -473,6 +584,25 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) writel_relaxed(1 << CCM_CCGR_OFFSET(0), base + 0x7c); writel_relaxed(0, base + 0x80); + /* Make sure PFDs are disabled at boot. */ + reg = readl_relaxed(anatop_base + 0x100); + /* Cannot disable pll2_pfd2_396M, as it is the MMDC clock in iMX6DL */ + if (cpu_is_imx6dl()) + reg |= 0x80008080; + else + reg |= 0x80808080; + writel_relaxed(reg, anatop_base + 0x100); + + /* Disable PLL3 PFDs. */ + reg = readl_relaxed(anatop_base + 0xF0); + reg |= 0x80808080; + writel_relaxed(reg, anatop_base + 0xF0); + + /* Make sure PLLs is disabled */ + reg = readl_relaxed(anatop_base + 0xA0); + reg &= ~(1 << 13); + writel_relaxed(reg, anatop_base + 0xA0); + clk_data.clks = clk; clk_data.clk_num = ARRAY_SIZE(clk); of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); @@ -489,11 +619,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk_register_clkdev(clk[lvds2_in], "lvds2_in", NULL); clk_register_clkdev(clk[esai], "esai", NULL); - if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) || cpu_is_imx6dl()) { - clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]); - clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]); - } - /* * The gpmi needs 100MHz frequency in the EDO/Sync mode, * We can not get the 100MHz from the pll2_pfd0_352m. @@ -507,7 +632,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) if (clk_set_parent(clk[pcie_axi_sel], clk[axi])) pr_err("Failed to set PCIe parent clk.\n"); - /* gpu clock initilazation */ clk_set_parent(clk[gpu3d_shader_sel], clk[pll2_pfd1_594m]); clk_set_rate(clk[gpu3d_shader], 594000000); @@ -524,8 +648,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) } /* ipu clock initialization */ - clk_set_parent(clk[ldb_di0_sel], clk[pll2_pfd0_352m]); - clk_set_parent(clk[ldb_di1_sel], clk[pll2_pfd0_352m]); + init_ldb_clks(pll2_pfd0_352m); clk_set_parent(clk[ipu1_di0_pre_sel], clk[pll5_video_div]); clk_set_parent(clk[ipu1_di1_pre_sel], clk[pll5_video_div]); clk_set_parent(clk[ipu2_di0_pre_sel], clk[pll5_video_div]); |