diff options
| author | Peter Zijlstra <peterz@infradead.org> | 2014-02-03 14:29:03 +0100 |
|---|---|---|
| committer | Jiri Slaby <jslaby@suse.cz> | 2015-01-10 12:40:17 +0100 |
| commit | 05d75f8aa3a9227b5180354671dff77c9a72d0bf (patch) | |
| tree | 848f6d23473d2b8cd2a20bca230dd3ee6b4107f1 | |
| parent | e1c34dac913e87ee8d03c06d7a328a7c2137cafb (diff) | |
perf/x86: Correctly use FEATURE_PDCM
commit c9b08884c9c98929ec2d8abafd78e89062d01ee7 upstream.
The current code simply assumes Intel Arch PerfMon v2+ to have
the IA32_PERF_CAPABILITIES MSR; the SDM specifies that we should check
CPUID[1].ECX[15] (aka, FEATURE_PDCM) instead.
This was found by KVM which implements v2+ but didn't provide the
capabilities MSR. Change the code to DTRT; KVM will also implement the
MSR and return 0.
Cc: pbonzini@redhat.com
Reported-by: "Michael S. Tsirkin" <mst@redhat.com>
Suggested-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/20140203132903.GI8874@twins.programming.kicks-ass.net
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Jiri Slaby <jslaby@suse.cz>
| -rw-r--r-- | arch/x86/kernel/cpu/perf_event_intel.c | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c index 02554ddf8481..b400d0be5b03 100644 --- a/arch/x86/kernel/cpu/perf_event_intel.c +++ b/arch/x86/kernel/cpu/perf_event_intel.c @@ -2288,10 +2288,7 @@ __init int intel_pmu_init(void) if (version > 1) x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3); - /* - * v2 and above have a perf capabilities MSR - */ - if (version > 1) { + if (boot_cpu_has(X86_FEATURE_PDCM)) { u64 capabilities; rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities); |