diff options
| author | Max Krummenacher <max.krummenacher@toradex.com> | 2016-03-01 16:05:30 +0100 |
|---|---|---|
| committer | Max Krummenacher <max.krummenacher@toradex.com> | 2016-03-09 10:01:53 +0100 |
| commit | f80a9b4090bcf9977dc0b6d2631281058c2d843c (patch) | |
| tree | dadf057ec1c1edb94ada241a141d2abfa993c10d | |
| parent | a56e97cbb75c0626cec7494cf58c9d795253a0a5 (diff) | |
mach-imx7d.c: use enet_out clk to decide on PHY clock
The i.MX 7 can provide a reference clock to the PHY or use a reference clock
from an external circuit.
If the device-tree node with compatible "fsl,imx7d-fec" has a clock named
enet_out then provide the clock from the i.MX 7, if such a clock is missing
use a clock provided from an external circuit.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
| -rw-r--r-- | arch/arm/mach-imx/mach-imx7d.c | 27 |
1 files changed, 25 insertions, 2 deletions
diff --git a/arch/arm/mach-imx/mach-imx7d.c b/arch/arm/mach-imx/mach-imx7d.c index fab9a0c584a6..1a417e9c4565 100644 --- a/arch/arm/mach-imx/mach-imx7d.c +++ b/arch/arm/mach-imx/mach-imx7d.c @@ -72,15 +72,38 @@ static void __init imx7d_enet_phy_init(void) static void __init imx7d_enet_clk_sel(void) { + struct device_node *np; + struct clk *enet_out_clk; struct regmap *gpr; + np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-fec"); + if (!np) { + pr_warn("%s: failed to find fec node\n", __func__); + return; + } + + enet_out_clk = of_clk_get_by_name(np, "enet_out"); + gpr = syscon_regmap_lookup_by_compatible("fsl,imx7d-iomuxc-gpr"); + if (!IS_ERR(gpr)) { - regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_TX_CLK_SEL_MASK, 0); - regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_CLK_DIR_MASK, IMX7D_GPR1_ENET1_CLK_DIR_MASK); + if (IS_ERR(enet_out_clk)) { + pr_info("%s: failed to get enet_out clock, assuming ext. clock source\n", __func__); + /* use external clock for PHY */ + regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_TX_CLK_SEL_MASK, IMX7D_GPR1_ENET_TX_CLK_SEL_MASK); + regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_CLK_DIR_MASK, 0); + } else { + pr_info("%s: found enet_out clock, assuming internal clock source\n", __func__); + /* use internal clock generation and output it to PHY */ + regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_TX_CLK_SEL_MASK, 0); + regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_CLK_DIR_MASK, IMX7D_GPR1_ENET1_CLK_DIR_MASK); + clk_put(enet_out_clk); + + } } else { pr_err("failed to find fsl,imx7d-iomux-gpr regmap\n"); } + of_node_put(np); } static inline void imx7d_enet_init(void) |