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authorPavan Kunapuli <pkunapuli@nvidia.com>2011-05-23 18:36:28 +0530
committerNiket Sirsi <nsirsi@nvidia.com>2011-05-25 15:19:02 -0700
commit29a0bbf8eb833879ea46d7af526e84706b2991c9 (patch)
treef454d121c1329d4ddc67d8cb19f13dbb739cb791
parentceb2e2c8b6a7d41c8917fcd49c7b0da745767931 (diff)
sdhci: tegra: Configure sdmmc drive strengths
Configure the pull up and pull down drive strengths for sdmmc. Bug 822057 Change-Id: Ic483f5311cdfdb6c35043ab33b5ff22462304de3 Reviewed-on: http://git-master/r/32607 Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com> Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
-rw-r--r--drivers/mmc/host/sdhci-tegra.c11
1 files changed, 10 insertions, 1 deletions
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index fc720711b6bc..bed414b4f5b8 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -56,6 +56,9 @@
#define SDMMC_AUTO_CAL_CONFIG 0x1E4
#define SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_ENABLE 0x20000000
+#define SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PD_OFFSET_SHIFT 0x8
+#define SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PD_OFFSET 0x70
+#define SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PU_OFFSET 0x62
#endif
struct tegra_sdhci_host {
@@ -213,8 +216,14 @@ static void tegra_sdhci_set_signalling_voltage(struct sdhci_host *sdhci,
/* Do Auto Calibration */
val = sdhci_readl(sdhci, SDMMC_AUTO_CAL_CONFIG);
val |= SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_ENABLE;
+ /* Program Auto cal PD offset(bits 8:14) */
+ val &= ~(0x7F << SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PD_OFFSET_SHIFT);
+ val |= (SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PD_OFFSET <<
+ SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PD_OFFSET_SHIFT);
+ /* Program Auto cal PU offset(bits 0:6) */
+ val &= ~0x7F;
+ val |= SDMMC_AUTO_CAL_CONFIG_AUTO_CAL_PU_OFFSET;
sdhci_writel(sdhci, val, SDMMC_AUTO_CAL_CONFIG);
-
}
#endif
}