diff options
| author | Stefan Agner <stefan@agner.ch> | 2016-03-22 15:45:29 -0700 |
|---|---|---|
| committer | Stefan Agner <stefan.agner@toradex.com> | 2016-03-28 10:53:32 -0700 |
| commit | e987c13431ffbfd52301dd031b1affc0a18c3f43 (patch) | |
| tree | 5b30c0d61614c80ac0ddb0035ec94798d1e08824 | |
| parent | d0171fbf707316a13a7de93624459abb130ca664 (diff) | |
drm/fsl-dcu: add extra clock for pixel clock
The Vybrid DCU variant has two independent clock inputs, one
for the registers (IPG bus clock) and one for the pixel clock.
Support this distinction in the DCU DRM driver while staying
backward compatible with devices providing only a single clock
(e.g. LS1021a SoC's).
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
| -rw-r--r-- | Documentation/devicetree/bindings/display/fsl,dcu.txt | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 16 | ||||
| -rw-r--r-- | drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h | 1 |
4 files changed, 19 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/display/fsl,dcu.txt b/Documentation/devicetree/bindings/display/fsl,dcu.txt index 8153c9a564b1..62c167e3da21 100644 --- a/Documentation/devicetree/bindings/display/fsl,dcu.txt +++ b/Documentation/devicetree/bindings/display/fsl,dcu.txt @@ -13,6 +13,8 @@ Required properties: Optional properties: - fsl,tcon: The phandle to the timing controller node. +- clocks: Second handle for pixel clock. +- clock-names: Second name "pix" for pixel clock. Examples: dcu: dcu@2ce0000 { diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c index afb303680f18..905728e84534 100644 --- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c +++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c @@ -143,7 +143,7 @@ static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) unsigned long dcuclk; index = drm_crtc_index(crtc); - dcuclk = clk_get_rate(fsl_dev->clk); + dcuclk = clk_get_rate(fsl_dev->pix_clk); div = dcuclk / mode->clock / 1000; /* Configure timings: */ diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c index 96bb48b870ef..36a2147648f4 100644 --- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c +++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c @@ -372,10 +372,21 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev) return ret; } + fsl_dev->pix_clk = devm_clk_get(dev, "pix"); + if (IS_ERR(fsl_dev->pix_clk)) { + /* legancy binding, use dcu clock as pixel clock */ + fsl_dev->pix_clk = fsl_dev->clk; + } + ret = clk_prepare_enable(fsl_dev->pix_clk); + if (ret < 0) { + dev_err(dev, "failed to enable pix clk\n"); + goto disable_clk; + } + drm = drm_dev_alloc(driver, dev); if (!drm) { ret = -ENOMEM; - goto disable_clk; + goto disable_pix_clk; } fsl_dev->tcon = fsl_tcon_init(dev); @@ -398,6 +409,8 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev) unref: drm_dev_unref(drm); +disable_pix_clk: + clk_disable_unprepare(fsl_dev->pix_clk); disable_clk: clk_disable_unprepare(fsl_dev->clk); return ret; @@ -408,6 +421,7 @@ static int fsl_dcu_drm_remove(struct platform_device *pdev) struct fsl_dcu_drm_device *fsl_dev = platform_get_drvdata(pdev); clk_disable_unprepare(fsl_dev->clk); + clk_disable_unprepare(fsl_dev->pix_clk); drm_put_dev(fsl_dev->drm); return 0; diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h index e1ee6efe5dc6..feef220a257c 100644 --- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h +++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h @@ -185,6 +185,7 @@ struct fsl_dcu_drm_device { struct regmap *regmap; int irq; struct clk *clk; + struct clk *pix_clk; struct fsl_tcon *tcon; /*protects hardware register*/ spinlock_t irq_lock; |