[ARM] outer_cache: add outer_restart callback and l2x0 implementation

outer_restart should be called by platform suspend_ops to restore
the outer cache to an active state following a power transition
which disables or otherwise invalidates the outer cache state.

Change-Id: I07a5268d1783fecd36491138e20913fca24a26d9
Reviewed-on: http://git-master/r/2243
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>

2 files changed, 30 insertions, 7 deletions

diff --git a/arch/arm/include/asm/outercache.h b/arch/arm/include/asm/outercache.h
index 30b265e12b2b..57bd2505046f 100644
--- a/arch/arm/include/asm/outercache.h
+++ b/arch/arm/include/asm/outercache.h
@@ -26,6 +26,7 @@ struct outer_cache_fns {
 	void (*clean_range)(unsigned long, unsigned long);
 	void (*flush_range)(unsigned long, unsigned long);
 	void (*shutdown)(void);
+	void (*restart)(void);
 #ifdef CONFIG_OUTER_CACHE_SYNC
 	void (*sync)(void);
 #endif
@@ -57,6 +58,12 @@ static inline void outer_shutdown(void)
 		outer_cache.shutdown();
 }
 
+static inline void outer_restart(void)
+{
+	if (outer_cache.restart)
+		outer_cache.restart();
+}
+
 #else
 
 static inline void outer_inv_range(unsigned long start, unsigned long end)
@@ -67,6 +74,8 @@ static inline void outer_flush_range(unsigned long start, unsigned long end)
 { }
 static inline void outer_shutdown(void)
 { }
+static inline void outer_restart(void)
+{ }
 
 #endif
 
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index cee0888514f7..8163e325f876 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -277,16 +277,12 @@ static void l2x0_shutdown(void)
 	local_irq_restore(flags);
 }
 
-void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
+static void l2x0_enable(__u32 aux_val, __u32 aux_mask)
 {
-	__u32 aux;
+	u32 aux;
 
-	if (l2x0_disabled) {
-		pr_info(L2CC_TYPE " cache controller disabled\n");
+	if (l2x0_disabled)
 		return;
-	}
-
-	l2x0_base = base;
 
 	/*
 	 * Check if l2x0 controller is already enabled.
@@ -307,12 +303,30 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
 		/* enable L2X0 */
 		writel(1, l2x0_base + L2X0_CTRL);
 	}
+}
+
+static void l2x0_restart(void)
+{
+	l2x0_enable(0, ~0ul);
+}
+
+void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
+{
+	if (l2x0_disabled) {
+		pr_info(L2CC_TYPE " cache controller disabled\n");
+		return;
+	}
+
+	l2x0_base = base;
+
+	l2x0_enable(aux_val, aux_mask);
 
 	outer_cache.inv_range = l2x0_inv_range;
 	outer_cache.clean_range = l2x0_clean_range;
 	outer_cache.flush_range = l2x0_flush_range;
 	outer_cache.sync = l2x0_cache_sync;
 	outer_cache.shutdown = l2x0_shutdown;
+	outer_cache.restart = l2x0_restart;
 
 	pr_info(L2CC_TYPE " cache controller enabled\n");
 }