diff options
author | Scott Williams <scwilliams@nvidia.com> | 2010-06-11 10:28:16 -0700 |
---|---|---|
committer | Gary King <gking@nvidia.com> | 2010-06-11 15:18:35 -0700 |
commit | ecbd9a2fe95aba341747b57db673dbc688fa13d0 (patch) | |
tree | 69ce9d96be1e62eeaac6b92114cd27a6c9d3a6af | |
parent | 52a8115b67a6f56306841a62c17d1ae1ae3f63f6 (diff) |
tegra: Avoid the use of literals in assembly code
Literals can be problematic in certain types of code.
Avoid them by taking advantage of ARMv7 architecture features.
This is a port of change 1255 from android-tegra-2.6.29.
Change-Id: I728177cd940a9524feca6bc1de7353a98dfc1878
Reviewed-on: http://git-master/r/2495
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
-rw-r--r-- | arch/arm/mach-tegra/cortex_a9_save.S | 14 | ||||
-rw-r--r-- | arch/arm/mach-tegra/delay.S | 3 | ||||
-rw-r--r-- | arch/arm/mach-tegra/headsmp.S | 12 |
3 files changed, 15 insertions, 14 deletions
diff --git a/arch/arm/mach-tegra/cortex_a9_save.S b/arch/arm/mach-tegra/cortex_a9_save.S index 791856e5e8db..4456f68c67d8 100644 --- a/arch/arm/mach-tegra/cortex_a9_save.S +++ b/arch/arm/mach-tegra/cortex_a9_save.S @@ -130,7 +130,7 @@ .macro ctx_ptr, rd, tmp cpu_id \tmp - ldr \rd, =tegra_context_area + mov32 \rd, tegra_context_area ldr \rd, [\rd] add \rd, \rd, \tmp, lsl #(CONTEXT_SIZE_WORDS_SHIFT+2) .endm @@ -219,12 +219,12 @@ ENTRY(__cortex_a9_save) str r1, [r8, #CTX_FPSCR] isb add r9, r8, #CTX_VFP_REGS - + VFPFSTMIA r9, r12 @ save out (16 or 32)*8B of FPU registers VFPFMXR FPEXC, r2 mrc p15, 0, r3, c1, c0, 2 @ restore original FPEXC/CPACR #endif - + add r9, r8, #CTX_TTBR0 mrc p15, 0, r0, c2, c0, 0 @ TTBR0 mrc p15, 0, r1, c2, c0, 1 @ TTBR1 @@ -273,7 +273,7 @@ ENTRY(__cortex_a9_save) cpu_id r4 cmp r4, #0 bne __cortex_a9_save_clean_cache - ldr r4, =(TEGRA_ARM_PL310_BASE-IO_CPU_PHYS+IO_CPU_VIRT) + mov32 r4, (TEGRA_ARM_PL310_BASE-IO_CPU_PHYS+IO_CPU_VIRT) add r9, r8, #CTX_L2_CTRL ldr r0, [r4, #L2X0_CTRL] ldr r1, [r4, #L2X0_AUX_CTRL] @@ -282,7 +282,7 @@ ENTRY(__cortex_a9_save) ldr r4, [r4, #L2X0_PREFETCH_OFFSET] stmia r9, {r0-r4} #endif - + __cortex_a9_save_clean_cache: mov r10, r8 @@ -303,7 +303,7 @@ __cortex_a9_save_clean_cache: mcr p15, 0, r0, c1, c0, 1 @ exit coherency isb cpu_id r0 - ldr r1, =(TEGRA_ARM_PERIF_BASE-IO_CPU_PHYS+IO_CPU_VIRT+0xC) + mov32 r1, (TEGRA_ARM_PERIF_BASE-IO_CPU_PHYS+IO_CPU_VIRT+0xC) mov r3, r0, lsl #2 mov r2, #0xf mov r2, r2, lsl r3 @@ -324,7 +324,7 @@ ENDPROC(__cortex_a9_save) ENTRY(__cortex_a9_l2x0_restart) #ifdef CONFIG_CACHE_L2X0 ctx_ptr r8, r9 - ldr r9, =(TEGRA_ARM_PL310_BASE-IO_CPU_PHYS+IO_CPU_VIRT) + mov32 r9, (TEGRA_ARM_PL310_BASE-IO_CPU_PHYS+IO_CPU_VIRT) add r10, r8, #CTX_L2_CTRL ldmia r10, {r3-r7} str r5, [r9, #L2X0_TAG_LATENCY_CTRL] diff --git a/arch/arm/mach-tegra/delay.S b/arch/arm/mach-tegra/delay.S index e8a4ff9793cb..3d9a7b30d4f3 100644 --- a/arch/arm/mach-tegra/delay.S +++ b/arch/arm/mach-tegra/delay.S @@ -22,12 +22,13 @@ #include <asm/cache.h> #include <mach/iomap.h> #include <mach/io.h> +#include "power-macros.S" .text ENTRY(__udelay) ENTRY(__const_udelay) - ldr r3, =(IO_PPSB_VIRT + TEGRA_TMRUS_BASE - IO_PPSB_PHYS) + mov32 r3, (IO_PPSB_VIRT + TEGRA_TMRUS_BASE - IO_PPSB_PHYS) ldr r1, [r3] /* r0 - usecs to wait diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S index d99404b67f5f..57fb8f56ef66 100644 --- a/arch/arm/mach-tegra/headsmp.S +++ b/arch/arm/mach-tegra/headsmp.S @@ -44,7 +44,7 @@ /* .section ".cpuinit.text", "ax"*/ .macro poke_ev, val, tmp - ldr \tmp, =(TEGRA_EXCEPTION_VECTORS_BASE + 0x100) + mov32 \tmp, (TEGRA_EXCEPTION_VECTORS_BASE + 0x100) str \val, [\tmp] .endm @@ -115,7 +115,7 @@ __invalidate_cpu_state: movne r2, #0xf movne r2, r2, lsl r0 strne r2, [r1] @ invalidate SCU tags for CPU - + dsb mov r0, #0x1800 mcr p15, 0, r0, c1, c0, 0 @ enable branch prediction, i-cache @@ -153,7 +153,7 @@ __return_to_virtual: mov lr, r1 @ "return" to ctx_restore mov r3, #0 mcr p15, 0, r3, c2, c0, 2 @ TTB control register - + mcr p15, 0, r8, c2, c0, 1 @ load TTBR1 mov r0, #0x1f @@ -213,11 +213,11 @@ ENDPROC(__turn_mmu_on_again) */ .align L1_CACHE_SHIFT __restart_pllx: - ldr r0, =tegra_sctx + mov32 r0, tegra_sctx ldr r1, [r0, #0x8] @ pllx_base ldr r2, [r0, #0xC] @ pllx_misc - ldr r3, =(TEGRA_CLK_RESET_BASE-IO_PPSB_PHYS+IO_PPSB_VIRT) - ldr r4, =(TEGRA_TMRUS_BASE-IO_PPSB_PHYS+IO_PPSB_VIRT) + mov32 r3, (TEGRA_CLK_RESET_BASE-IO_PPSB_PHYS+IO_PPSB_VIRT) + mov32 r4, (TEGRA_TMRUS_BASE-IO_PPSB_PHYS+IO_PPSB_VIRT) str r2, [r3, #0xe4] @ pllx_misc str r1, [r3, #0xe0] @ pllx_base /* record the time that PLLX will be stable */ |