imx6dl: Implemented creation of cameras video device.

Signed-off-by: Dmitry Lavnikevich <d.lavnikevich@sam-solutions.net>

2 files changed, 67 insertions, 7 deletions

diff --git a/arch/arm/mach-mx6/board-mx6dl_phyflex.h b/arch/arm/mach-mx6/board-mx6dl_phyflex.h
index f2ad9316e18f..3c1464111662 100644
--- a/arch/arm/mach-mx6/board-mx6dl_phyflex.h
+++ b/arch/arm/mach-mx6/board-mx6dl_phyflex.h
@@ -20,6 +20,13 @@
 #define _BOARD_MX6DL_PHYFLEX_H
 #include <mach/iomux-mx6dl.h>
 
+#define PHYFLEX_MX6DL_CLKO_PAD_CTRL	(PAD_CTL_SPEED_MED | PAD_CTL_DSE_34ohm | \
+		PAD_CTL_SRE_FAST)
+
+#define  PHYFLEX_MX6DL_PAD_GPIO_5__CCM_CLKO		\
+		(MX6DL_PAD_GPIO_5__CCM_CLKO | MUX_PAD_CTRL(PHYFLEX_CLKO_PAD_CTRL))
+
+
 static iomux_v3_cfg_t mx6dl_phyflex_pads[] = {
 
 	/* GPIOs for revision control */
@@ -145,6 +152,50 @@ static iomux_v3_cfg_t mx6dl_phyflex_pads[] = {
 	MX6DL_PAD_KEY_COL3__HDMI_TX_DDC_SCL,
 	MX6DL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA,
 	MX6DL_PAD_EIM_A25__HDMI_TX_CEC_LINE,
+
+	/* ipu1 csi0 */
+	MX6DL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC,
+	MX6DL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK,
+	MX6DL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC,
+	MX6DL_PAD_CSI0_DATA_EN__GPIO_5_20,
+	PHYFLEX_MX6DL_PAD_GPIO_5__CCM_CLKO,
+	MX6DL_PAD_ENET_RX_ER__GPIO_1_24,
+	MX6DL_PAD_CSI0_DAT10__IPU1_CSI0_D_10,
+	MX6DL_PAD_CSI0_DAT11__IPU1_CSI0_D_11,
+	MX6DL_PAD_CSI0_DAT12__IPU1_CSI0_D_12,
+	MX6DL_PAD_CSI0_DAT13__IPU1_CSI0_D_13,
+	MX6DL_PAD_CSI0_DAT14__IPU1_CSI0_D_14,
+	MX6DL_PAD_CSI0_DAT15__IPU1_CSI0_D_15,
+	MX6DL_PAD_CSI0_DAT16__IPU1_CSI0_D_16,
+	MX6DL_PAD_CSI0_DAT17__IPU1_CSI0_D_17,
+	MX6DL_PAD_CSI0_DAT18__IPU1_CSI0_D_18,
+	MX6DL_PAD_CSI0_DAT19__IPU1_CSI0_D_19,
+
+	/* ipu1 csi1 */
+	MX6DL_PAD_EIM_A16__IPU1_CSI1_PIXCLK,
+	MX6DL_PAD_EIM_DA11__IPU1_CSI1_HSYNC,
+	MX6DL_PAD_EIM_DA12__IPU1_CSI1_VSYNC,
+	MX6DL_PAD_EIM_DA10__GPIO_3_10,
+	MX6DL_PAD_EIM_DA9__IPU1_CSI1_D_0,
+	MX6DL_PAD_EIM_DA8__IPU1_CSI1_D_1,
+	MX6DL_PAD_EIM_DA7__IPU1_CSI1_D_2,
+	MX6DL_PAD_EIM_DA6__IPU1_CSI1_D_3,
+	MX6DL_PAD_EIM_DA5__IPU1_CSI1_D_4,
+	MX6DL_PAD_EIM_DA4__IPU1_CSI1_D_5,
+	MX6DL_PAD_EIM_DA3__IPU1_CSI1_D_6,
+	MX6DL_PAD_EIM_DA2__IPU1_CSI1_D_7,
+	MX6DL_PAD_EIM_DA1__IPU1_CSI1_D_8,
+	MX6DL_PAD_EIM_DA0__IPU1_CSI1_D_9,
+	MX6DL_PAD_EIM_EB1__IPU1_CSI1_D_10,
+	MX6DL_PAD_EIM_EB0__GPIO_2_28,
+	MX6DL_PAD_EIM_A17__IPU1_CSI1_D_12,
+	MX6DL_PAD_EIM_A18__IPU1_CSI1_D_13,
+	MX6DL_PAD_EIM_A19__IPU1_CSI1_D_14,
+	MX6DL_PAD_EIM_A20__IPU1_CSI1_D_15,
+	MX6DL_PAD_EIM_A21__IPU1_CSI1_D_16,
+	MX6DL_PAD_EIM_A22__IPU1_CSI1_D_17,
+	MX6DL_PAD_EIM_A23__IPU1_CSI1_D_18,
+	MX6DL_PAD_EIM_A24__IPU1_CSI1_D_19,
 };
 
 #endif  /* _BOARD_MX6DL_PHYFLEX_H */
diff --git a/arch/arm/mach-mx6/board-mx6q_phyflex.c b/arch/arm/mach-mx6/board-mx6q_phyflex.c
index e22a1a4ebfde..967459831310 100644
--- a/arch/arm/mach-mx6/board-mx6q_phyflex.c
+++ b/arch/arm/mach-mx6/board-mx6q_phyflex.c
@@ -1001,15 +1001,15 @@ static struct mxc_camera_pdata mxc_ipu_csi_pdata[] = {
 		.ipu = 0,
 		.csi = 0,
 		.mclk_default_rate = 27000000,
-		.mclk_target_rate = 60000000,	//only for mt9p031
-		.use_pll = 0,					//only for mt9p031
+		.mclk_target_rate = 60000000,	/* only for mt9p031 */
+		.use_pll = 0,			/* only for mt9p031 */
 	}, {
 		.flags = MXC_CAMERA_DATAWIDTH_10,
-		.ipu = 1,
+		.ipu = 1, /* changes to 0 in runtame for mx6dl and mx6sl */
 		.csi = 1,
 		.mclk_default_rate = 27000000,
-		.mclk_target_rate = 60000000,	//only for mt9p031
-		.use_pll = 0,					//only for mt9p031
+		.mclk_target_rate = 60000000,	/* only for mt9p031 */
+		.use_pll = 0,					/* only for mt9p031 */
 	},
 };
 
@@ -1078,7 +1078,7 @@ static struct fsl_mxc_capture_platform_data capture_data[] = {
 	},
 	[1] = {
 		.csi = 1,
-		.ipu = 1,
+		.ipu = 1, /*changes to 0 in runtame for mx6dl and mx6sl */
 		.mclk_source = 0,
 		.is_mipi = 0,
 	},
@@ -1167,6 +1167,15 @@ static void __init mx6_phyflex_init(void)
 
 	long csi0_cam_address_hex;
 	long csi1_cam_address_hex;
+
+	/* i.MX6 DL and SL processors contain only one IPU - correct
+	 * default configuration in structures that use 1st IPU */
+	if (cpu_is_mx6dl() || cpu_is_mx6sl()) {
+		mxc_ipu_csi_pdata[1].ipu = 0;
+#ifndef CONFIG_SOC_CAMERA
+		&capture_data[1].ipu = 0;
+#endif
+	}
 	
 	if (cpu_is_mx6q()) {
 		 mxc_iomux_v3_setup_multiple_pads(mx6q_phytec_common_pads,
@@ -1238,7 +1247,7 @@ static void __init mx6_phyflex_init(void)
 
 	imx6q_add_v4l2_output(0);
 
-if(cpu_is_mx6q()) {	
+if(cpu_is_mx6q() || cpu_is_mx6dl()) {	
 	/***************************************************************************
 	Camera section:
 	The bootargs csi0 and csi1 will be interpreted.