ENGR00275391 i.mx6d/q: disable the double linefill feature of PL310

The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
But according to ARM PL310 errata: 752271
ID: 752271: Double linefill feature can cause data corruption
Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
Workaround: The only workaround to this erratum is to disable the
double linefill feature. This is the default behavior.

[in the commit:c483abdca0011c1342bad42f16925dd5a2c7c091]
ENGR00271977-1 imx6_defconfig: enable PL310_ERRATA_769419

There is one error in the commit log, the correct PL310 version in
i.MX6DL/SOLO should be r3p2, not r3p1-50rel0.

so, PL310_ERRATA_769419, will not apply to i.MX6DL/SOLO. But since we build
one image to support both i.MX6Q and i.MX6DL/SOLO, the ideal solution is to
manage this errata in dynamic way. Someone did post the patches here:
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-January/145593.html

As the discussion on the above link, Russell King, the ARM arch maintainer said:

"As I already said, there is _no_ point making the barrier conditional;
it's probably more expensive to make it conditional than just to execute
it every time.  But we still might as well optimize it away if we are
running _only_ on platforms which _do_ _not_ have that errata."

So, we will turn on the PL310_ERRATA_769419 on both i.MX6D/Q and i.MX6DL/SOLO.

Signed-off-by: Jason Liu <r64343@freescale.com>

1 files changed, 15 insertions, 3 deletions

diff --git a/arch/arm/mach-mx6/mm.c b/arch/arm/mach-mx6/mm.c
index 3cf6b226fca6..8d2c715f336b 100644
--- a/arch/arm/mach-mx6/mm.c
+++ b/arch/arm/mach-mx6/mm.c
@@ -111,9 +111,21 @@ int mxc_init_l2x0(void)
 	writel(0x132, IO_ADDRESS(L2_BASE_ADDR + L2X0_TAG_LATENCY_CTRL));
 	writel(0x132, IO_ADDRESS(L2_BASE_ADDR + L2X0_DATA_LATENCY_CTRL));
 
-	val = readl(IO_ADDRESS(L2_BASE_ADDR + L2X0_PREFETCH_CTRL));
-	val |= 0x40800000;
-	writel(val, IO_ADDRESS(L2_BASE_ADDR + L2X0_PREFETCH_CTRL));
+	/*
+	 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
+	 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
+	 * But according to ARM PL310 errata: 752271
+	 * ID: 752271: Double linefill feature can cause data corruption
+	 * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
+	 * Workaround: The only workaround to this erratum is to disable the
+	 * double linefill feature. This is the default behavior.
+	 */
+	if (!cpu_is_mx6q()) {
+		val = readl(IO_ADDRESS(L2_BASE_ADDR + L2X0_PREFETCH_CTRL));
+		val |= 0x40800000;
+		writel(val, IO_ADDRESS(L2_BASE_ADDR + L2X0_PREFETCH_CTRL));
+	}
+
 	val = readl(IO_ADDRESS(L2_BASE_ADDR + L2X0_POWER_CTRL));
 	val |= L2X0_DYNAMIC_CLK_GATING_EN;
 	val |= L2X0_STNDBY_MODE_EN;