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authorChristian Hemp <c.hemp@phytec.de>2013-08-13 08:09:10 +0200
committerJustin Waters <justin.waters@timesys.com>2013-11-07 12:19:36 -0500
commite216ae3f8830d3bb69675c6cb82984d05dda43ea (patch)
tree259d2c5ac6248845e52d983266eeb4d6b7a1e566
parentdaf2b5fd0a51ffdcd013a50c7dc56fcd606b31d8 (diff)
imx6:phyflex: Add NAND muxing for dual an single core
Signed-off-by: Christian Hemp <c.hemp@phytec.de>
-rw-r--r--arch/arm/mach-mx6/board-mx6q_phytec-nand.c35
1 files changed, 33 insertions, 2 deletions
diff --git a/arch/arm/mach-mx6/board-mx6q_phytec-nand.c b/arch/arm/mach-mx6/board-mx6q_phytec-nand.c
index 96647fc4aaf8..69d7877feeac 100644
--- a/arch/arm/mach-mx6/board-mx6q_phytec-nand.c
+++ b/arch/arm/mach-mx6/board-mx6q_phytec-nand.c
@@ -21,6 +21,7 @@
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx6q.h>
+#include <mach/iomux-mx6dl.h>
#include "devices-imx6q.h"
#include "crm_regs.h"
@@ -79,16 +80,46 @@ static iomux_v3_cfg_t mx6q_gpmi_nand_rev2[] __initdata = {
MX6Q_PAD_SD4_DAT0__RAWNAND_DQS,
};
+static iomux_v3_cfg_t mx6dl_gpmi_nand_rev2[] __initdata = {
+ MX6DL_PAD_NANDF_CLE__RAWNAND_CLE,
+ MX6DL_PAD_NANDF_ALE__RAWNAND_ALE,
+ MX6DL_PAD_NANDF_CS0__RAWNAND_CE0N,
+ MX6DL_PAD_NANDF_CS1__RAWNAND_CE1N,
+ MX6DL_PAD_NANDF_CS3__RAWNAND_CE3N,
+ MX6DL_PAD_NANDF_RB0__RAWNAND_READY0,
+ MX6DL_PAD_SD4_DAT0__RAWNAND_DQS,
+ MX6DL_PAD_NANDF_D0__RAWNAND_D0,
+ MX6DL_PAD_NANDF_D1__RAWNAND_D1,
+ MX6DL_PAD_NANDF_D2__RAWNAND_D2,
+ MX6DL_PAD_NANDF_D3__RAWNAND_D3,
+ MX6DL_PAD_NANDF_D4__RAWNAND_D4,
+ MX6DL_PAD_NANDF_D5__RAWNAND_D5,
+ MX6DL_PAD_NANDF_D6__RAWNAND_D6,
+ MX6DL_PAD_NANDF_D7__RAWNAND_D7,
+ MX6DL_PAD_SD4_CLK__RAWNAND_WRN,
+ MX6DL_PAD_NANDF_WP_B__RAWNAND_RESETN,
+};
+
static int __init gpmi_nand_platform_init(void)
{
int ret;
if (module_rev == PHYFLEX_MODULE_REV_1) {
- ret = mxc_iomux_v3_setup_multiple_pads(mx6q_gpmi_nand,
+ if (cpu_is_mx6q()) {
+ ret = mxc_iomux_v3_setup_multiple_pads(mx6q_gpmi_nand,
ARRAY_SIZE(mx6q_gpmi_nand));
+ } else if (cpu_is_mx6dl()) {
+ ret = mxc_iomux_v3_setup_multiple_pads(mx6dl_gpmi_nand_rev2,
+ ARRAY_SIZE(mx6dl_gpmi_nand_rev2));
+ }
} else {
- ret = mxc_iomux_v3_setup_multiple_pads(mx6q_gpmi_nand_rev2,
+ if (cpu_is_mx6q()) {
+ ret = mxc_iomux_v3_setup_multiple_pads(mx6q_gpmi_nand_rev2,
ARRAY_SIZE(mx6q_gpmi_nand_rev2));
+ } else if (cpu_is_mx6dl()) {
+ ret = mxc_iomux_v3_setup_multiple_pads(mx6dl_gpmi_nand_rev2,
+ ARRAY_SIZE(mx6dl_gpmi_nand_rev2));
+ }
}
return ret;