diff options
| author | Anson Huang <Anson.Huang@nxp.com> | 2016-10-11 00:20:59 +0800 |
|---|---|---|
| committer | Anson Huang <Anson.Huang@nxp.com> | 2017-06-08 19:25:03 +0800 |
| commit | 89bce7489eb1d0b7b6f2bf7c2083d4c92472aff2 (patch) | |
| tree | c6d7d57f5098f6fefa9955f95db8db6e9b9ebe49 | |
| parent | 1ebdced8f2bb1b4c0be430fa4f84e0af413872f4 (diff) | |
MLK-13306-1 ARM: imx: correct ddr type for i.mx6sll
For MMDC, LPDDR3 type's value is 2b'11, which is
different from DDRC, so correct it.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
| -rw-r--r-- | arch/arm/mach-imx/anatop.c | 10 | ||||
| -rw-r--r-- | arch/arm/mach-imx/mxc.h | 1 | ||||
| -rw-r--r-- | arch/arm/mach-imx/pm-imx6.c | 2 |
3 files changed, 8 insertions, 5 deletions
diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c index abdc3c53554d..fe4fda991045 100644 --- a/arch/arm/mach-imx/anatop.c +++ b/arch/arm/mach-imx/anatop.c @@ -68,7 +68,8 @@ static void imx_anatop_enable_weak2p5(bool enable) regmap_read(anatop, ANADIG_ANA_MISC0, &val); - if (cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull()) + if (cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() + || cpu_is_imx6sll()) mask = BM_ANADIG_ANA_MISC0_V3_STOP_MODE_CONFIG; else if (cpu_is_imx6sl()) mask = BM_ANADIG_ANA_MISC0_V2_STOP_MODE_CONFIG; @@ -95,7 +96,8 @@ static inline void imx_anatop_enable_2p5_pulldown(bool enable) static inline void imx_anatop_disconnect_high_snvs(bool enable) { - if (cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull()) + if (cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() || + cpu_is_imx6sll()) regmap_write(anatop, ANADIG_ANA_MISC0 + (enable ? REG_SET : REG_CLR), BM_ANADIG_ANA_MISC0_V2_DISCON_HIGH_SNVS); @@ -147,7 +149,7 @@ void imx_anatop_pre_suspend(void) imx_anatop_disable_pu(true); if ((imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2 || - imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR3) && + imx_mmdc_get_ddr_type() == IMX_MMDC_DDR_TYPE_LPDDR3) && !imx_gpc_usb_wakeup_enabled()) imx_anatop_enable_2p5_pulldown(true); else @@ -177,7 +179,7 @@ void imx_anatop_post_resume(void) imx_anatop_disable_pu(false); if ((imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2 || - imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR3) && + imx_mmdc_get_ddr_type() == IMX_MMDC_DDR_TYPE_LPDDR3) && !imx_gpc_usb_wakeup_enabled()) imx_anatop_enable_2p5_pulldown(false); else diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h index f285b5457b1c..60aaec2a4b97 100644 --- a/arch/arm/mach-imx/mxc.h +++ b/arch/arm/mach-imx/mxc.h @@ -46,6 +46,7 @@ #define IMX_DDR_TYPE_DDR3 0 #define IMX_DDR_TYPE_LPDDR2 1 #define IMX_DDR_TYPE_LPDDR3 2 +#define IMX_MMDC_DDR_TYPE_LPDDR3 3 #ifndef __ASSEMBLY__ extern unsigned int __mxc_cpu_type; diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c index 06f00d442a63..6b3b53555601 100644 --- a/arch/arm/mach-imx/pm-imx6.c +++ b/arch/arm/mach-imx/pm-imx6.c @@ -1133,7 +1133,7 @@ static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata) mmdc_offset_array[i]); } - if (cpu_is_imx6sll() && pm_info->ddr_type == IMX_DDR_TYPE_LPDDR3) { + if (cpu_is_imx6sll() && pm_info->ddr_type == IMX_MMDC_DDR_TYPE_LPDDR3) { pm_info->mmdc_val[0][1] = 0x8000; pm_info->mmdc_val[2][1] = 0xa1390003; pm_info->mmdc_val[3][1] = 0x470000; |