diff options
| author | Antti P Miettinen <amiettinen@nvidia.com> | 2013-10-13 22:52:35 +0300 |
|---|---|---|
| committer | Gabby Lee <galee@nvidia.com> | 2014-01-14 03:02:27 -0800 |
| commit | d84e7b7804a0cf21d7ec6a2ded6054c932c5e15b (patch) | |
| tree | e2edf8fd2fe1c76cee310a0f57bf03af06b0459c | |
| parent | 372e30250fda1a4dc08bd9ca5997b76c6ae5e170 (diff) | |
ARM: Tegra: Utilize burst policy for LP1 wakeup
Running SCLK from CLKS makes LP1 wakeup latencies horrible.
However, we can utilize IRQ bursting to switch automatically
to CLKM upon LP1 wakeup IRQ. This maintains low power for LP1
but improves wakeup latencies significantly.
Bug 1381343
Change-Id: I9a3fcd81999d1b593bf242bfa7ef8505f9848d43
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/298749
(cherry picked from commit 39d6266e1ed04512809badb263a6d9b4346a49e4)
Reviewed-on: http://git-master/r/298744
(cherry picked from commit 12a25b041874515a7076b30f1462a12756d75d16)
(cherry picked from commit b90f85660ac259da9190cce156763fb05caa5f82)
Reviewed-on: http://git-master/r/353758
Reviewed-by: Gabby Lee <galee@nvidia.com>
Tested-by: Gabby Lee <galee@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/pm.c | 1 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/sleep-t3.S | 16 |
2 files changed, 11 insertions, 6 deletions
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index ec13b2a11af8..306d4c966f76 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -1284,6 +1284,7 @@ void __init tegra_init_suspend(struct tegra_suspend_platform_data *plat) BUG_ON(IS_ERR(tegra_pclk)); tegra_clk_m = clk_get_sys(NULL, "clk_m"); + BUG_ON(IS_ERR(tegra_clk_m)); pdata = plat; (void)reg; (void)mode; diff --git a/arch/arm/mach-tegra/sleep-t3.S b/arch/arm/mach-tegra/sleep-t3.S index bf32445de42c..6f491fddbbef 100644 --- a/arch/arm/mach-tegra/sleep-t3.S +++ b/arch/arm/mach-tegra/sleep-t3.S @@ -440,9 +440,9 @@ tegra3_iram_start: ENTRY(tegra3_lp1_reset) /* the CPU and system bus are running from CLKM and executing from - * IRAM when this code is executed - * switch all SCLK/CCLK clocks to CLKM and set non STDBY clock source - * enable PLLP, PLLM, PLLC, and PLLX. */ + * IRAM when this code is executed + * switch all SCLK/CCLK clocks to CLKM and set non STDBY clock source + * enable PLLP, PLLM, PLLC, and PLLX. */ mov32 r0, TEGRA_CLK_RESET_BASE #ifndef CONFIG_TRUSTED_FOUNDATIONS /* secure code handles 32KHz to CLKM/OSC clock switch */ @@ -779,7 +779,7 @@ tegra3_tear_down_core: * tegra3_cpu_clk32k * * In LP0 and LP1 all plls will be turned off. Switch the system clock - * to the 32khz clock (clks) and CPU to clkm. + * to the 32khz clock (clks) * r4 = TEGRA_PMC_BASE * r5 = TEGRA_CLK_RESET_BASE * r6 = TEGRA_FLOW_CTRL_BASE @@ -889,8 +889,12 @@ powerdown_pll_cx: str r0, [r5, #CLK_RESET_SCLK_BURST] mov pc, lr - /* switch to CLKS */ - mov r0, #0 /* burst policy = 32KHz */ + /* + * Switch to STDBY clock (CLKS), bits 28:31 == 0 + * Enable burst on CPU IRQ (bit 24) + * Set clock sources to CLKM (clock source 0) + */ + mov r0, #(1 << 24) str r0, [r5, #CLK_RESET_SCLK_BURST] mov pc, lr |