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authorSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>2014-01-23 23:38:04 +0100
committerJiri Slaby <jslaby@suse.cz>2014-03-05 17:13:52 +0100
commitdd14a330306a608820bb7eb4983443e6145483c7 (patch)
treeacc5feedb15089f723ea0684c53a03e0b697a9ad
parentde77ab8e1e55506d0e8759a13416935f5d0c8bc6 (diff)
irqchip: orion: clear bridge cause register on init
commit 7b119fd1bdc59a8060df5b659b9f7a70e0169fd6 upstream. It is good practice to mask and clear pending irqs on init. We already mask all irqs, so also clear the bridge irq cause register. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Jiri Slaby <jslaby@suse.cz>
-rw-r--r--drivers/irqchip/irq-orion.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/irqchip/irq-orion.c b/drivers/irqchip/irq-orion.c
index e51d40031884..4137c3d15284 100644
--- a/drivers/irqchip/irq-orion.c
+++ b/drivers/irqchip/irq-orion.c
@@ -180,8 +180,9 @@ static int __init orion_bridge_irq_init(struct device_node *np,
gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
- /* mask all interrupts */
+ /* mask and clear all interrupts */
writel(0, gc->reg_base + ORION_BRIDGE_IRQ_MASK);
+ writel(0, gc->reg_base + ORION_BRIDGE_IRQ_CAUSE);
irq_set_handler_data(irq, domain);
irq_set_chained_handler(irq, orion_bridge_irq_handler);