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authorShardar Shariff Md <smohammed@nvidia.com>2014-02-21 20:02:53 +0530
committerLaxman Dewangan <ldewangan@nvidia.com>2014-02-24 00:53:03 -0800
commit199c6c12ab4d564d2c732e67771ba6e5cb3fb909 (patch)
treed0eeda0bfe11115899e9a23101c2b978b3a79527
parent7fc15f0d8b721054e849db4261ba9f1a9157f103 (diff)
arm: tegra: spi:Increase transfer timeout to 10sec
Increasing transfer timeout from 1sec to 10sec as timeout issue is happening during stress tests sporadically, this timeout is root caused due to delay in SPI ISR thread switch. Bug 1451201 Change-Id: I1b500590875548b618139855cce8a9f4dcdac186 Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com> Reviewed-on: http://git-master/r/372903 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
-rw-r--r--drivers/spi/spi-tegra114.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
index 78849b072321..eed73d798d7a 100644
--- a/drivers/spi/spi-tegra114.c
+++ b/drivers/spi/spi-tegra114.c
@@ -159,7 +159,7 @@
#define DATA_DIR_TX (1 << 0)
#define DATA_DIR_RX (1 << 1)
-#define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000))
+#define SPI_DMA_TIMEOUT (msecs_to_jiffies(10000))
#define DEFAULT_SPI_DMA_BUF_LEN (16*1024)
#define TX_FIFO_EMPTY_COUNT_MAX SPI_TX_FIFO_EMPTY_COUNT(0x40)
#define RX_FIFO_FULL_COUNT_ZERO SPI_RX_FIFO_FULL_COUNT(0)