diff options
| author | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-02 16:49:01 -0700 |
|---|---|---|
| committer | Simone Willett <swillett@nvidia.com> | 2012-04-05 17:57:47 -0700 |
| commit | bd1e9de741fa7578062e93bda5251b95ac0f9d24 (patch) | |
| tree | 2f1c7f6759c68c58d34f956996249fb5a09eaa74 | |
| parent | a27cd62bb4934abe2af420ba7ca5115fbfb653be (diff) | |
Revert "ARM: tegra: power: Workaround PMD corruption by cpu_resume_mmu"
This reverts commit 48565a367997c1748c655bc834e06b348d4e5b2c.
Change-Id: I0e1411f1260ae916c510478276d88b41416a0d42
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/85670
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/sleep.S | 21 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/sleep.h | 41 |
2 files changed, 23 insertions, 39 deletions
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S index 973c8677bafe..003de98acd03 100644 --- a/arch/arm/mach-tegra/sleep.S +++ b/arch/arm/mach-tegra/sleep.S @@ -395,6 +395,27 @@ tegra_cpu_resume: * r1 = physical address to jump to with mmu off */ ENTRY(tegra_turn_off_mmu) + /* + * change page table pointer to tegra_pgd_phys, so that IRAM + * and MMU shut-off will be mapped virtual == physical + */ + mrc p15, 0, r2, c2, c0, 0 @ TTB 0 + mov32 r3, ~PAGE_MASK + and r2, r2, r3 + ldr r3, tegra_pgd_phys_address + ldr r3, [r3] + orr r3, r3, r2 + mov r2, #0 + mcr p15, 0, r2, c13, c0, 1 @ reserved context + isb + mcr p15, 0, r3, c2, c0, 0 @ TTB 0 + isb + + mov r2, #0 + mcr p15, 0, r2, c8, c3, 0 @ invalidate TLB + mcr p15, 0, r2, c7, c5, 6 @ flush BTAC + mcr p15, 0, r2, c7, c5, 0 @ flush instruction cache + mov32 r3, tegra_shut_off_mmu add r3, r3, r0 mov r0, r1 diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h index 2557c3f687a8..b27dd48cebda 100644 --- a/arch/arm/mach-tegra/sleep.h +++ b/arch/arm/mach-tegra/sleep.h @@ -131,54 +131,17 @@ .macro push_ctx_regs, tmp1 push_stack_token \tmp1 @ debug check word stmfd sp!, {r4 - r11, lr} - /* Save the current TTB0 and CONTEXTID registers. */ - mrc p15, 0, r5, c2, c0, 0 @ TTB 0 - mrc p15, 0, r6, c13, c0, 1 @ CONTEXTID #if USE_TEGRA_DIAG_REG_SAVE mrc p15, 0, r4, c15, c0, 1 @ read diagnostic register - stmfd sp!, {r4-r6} -#else - stmfd sp!, {r5-r6} + stmfd sp!, {r4} #endif - /* Switch to the tegra_pgd so that IRAM and the MMU shut-off code - will be flat mapped (VA==PA). We also do this because the common - ARM CPU state save/restore code doesn't support an external L2 - cache controller. If the current PGD is left active, the common - ARM MMU restore may (and eventually will) damage the currently - running page tables by adding a temporary flat section mapping - that could be picked up by other CPUs from the L2 cache - resulting in a kernel panic. */ - ldr r6, tegra_pgd_phys_address - ldr r6, [r6] - mov r7, #0 - dsb - mcr p15, 0, r7, c13, c0, 1 @ CONTEXTID = reserved context - isb - mcr p15, 0, r6, c2, c0, 0 @ TTB 0 - isb - mcr p15, 0, r7, c8, c3, 0 @ invalidate TLB - mcr p15, 0, r7, c7, c5, 6 @ flush BTAC - mcr p15, 0, r7, c7, c5, 0 @ flush instruction cache - dsb .endm .macro pop_ctx_regs, tmp1, tmp2 #if USE_TEGRA_DIAG_REG_SAVE - ldmfd sp!, {r4-r6} + ldmfd sp!, {r4} mcr p15, 0, r4, c15, c0, 1 @ write diagnostic register -#else - ldmfd sp!, {r5-r6} #endif - dsb - mcr p15, 0, r5, c2, c0, 0 @ TTB 0 - isb - mcr p15, 0, r6, c13, c0, 1 @ CONTEXTID = reserved context - isb - mov r7, #0 - mcr p15, 0, r7, c8, c3, 0 @ invalidate TLB - mcr p15, 0, r7, c7, c5, 6 @ flush BTAC - mcr p15, 0, r7, c7, c5, 0 @ flush instruction cache - dsb ldmfd sp!, {r4 - r11, lr} pop_stack_token \tmp1, \tmp2 @ debug stack debug token .endm |