ARM: tegra: Add suspend support

Tegra supports three low power modes that involve powering down the CPU.

LP2 powers down both CPU cores and the GICs, but leaves the core
peripherals, including the memory controller and the legacy
interrupt controller, enabled.  The legacy interrupt controller
is used as the wakeup source, and any interrupt can wake the device.
LP2 can be used in idle.

LP1 is the same as LP2, but in addition turns off the memory
controller and puts the DDR memory in self-refresh.  Any interrupt
can wake the device. LP1 could be used in idle if no peripherals
are doing DMA.

LP0 turns off everything in the SoC except the RTC and a power
management controller, both of which run off a 32 kHz clock.
The power management controller has 32 wake sources, all other
interrupts can not be used to wake from LP0.

These low power modes power-gate the main CPU complex, requiring a
full processor state save and restore from a reset vector.

Platform-specific data (power good times, PMU capabilities, etc.) must be
specified when registering the suspend operations to ensure that platform
power sequencing restrictions are maintained.

In both LP0 and LP1, SDRAM is placed into self-refresh. in order to safely
perform this transition, the final shutdown procedure responsible for

  * turning off the MMU and L1 data cache
  * putting memory into self-refresh
  * setting the DDR pads to the lowest power state
  * and turning off PLLs

is copied into IRAM (at the address TEGRA_IRAM_BASE + SZ_4K) at the
start of the suspend process.

In LP1 mode (like LP2), the CPU is reset and executes the code specified
at the EVP reset vector.  Since SDRAM is in self-refresh, this code must
also be located in IRAM, and it must re-enable DRAM before restoring the
full context.  In this implementation, it enables the CPU on PLLP, enables
PLLC and PLLM, restores the SCLK burst policy, and jumps to the LP2 reset
vector to restore the rest of the system (MMU, PLLX, coresite, etc.).  The
LP2 reset vector is expected to be found in PMC_SCRATCH1, and is
initialized during system-bootup.

In LP0 mode, the core voltage domain is also shutoff.  As a result, all
of the volatile state in the core voltage domain (e.g., pinmux registers,
clock registers, etc.) must be saved to memory so that it can be restored
after the system resumes.  A limited set of wakeups are available from LP0,
and the correct levels for the wakeups must be programmed into the PMC
wakepad configuration register prior to system shutdown.  On resume, the
system resets into the boot ROM, and the boot ROM restores SDRAM and other
system state using values saved during kernel initialization in the PMC
scratch registers.

Resuming from LP0 requires the boot ROM to supply a signed recovery codeblob
to the kernel; the kernel expects that the length and address of this blob
is supplied with the lp0_vec= command line argument; if not present, suspend-
to-LP0 will be disabled

For simplicity, the outer cache is shutdown for both LP0 and LP1; it
is possible to optimize the LP1 routine to bypass outer cache shutdown
and restart.

Includes fixes from:
Scott Williams <scwilliams@nvidia.com>
Aleksandr Frid <afrid@nvidia.com>
Vik Kasivajhula <tkasivajhula@nvidia.com>
Bharat Nihalani <Kbnihalani@nvidia.com>
James Wylder <james.wylder@motorola.com>
Allen Martin <amartin@nvidia.com>

Change-Id: I9e4e61c2fbb8c7bb5a29b1832ea38e7ea0524c52
Original-author: Gary King <gking@nvidia.com>
Signed-off-by: Gary King <gking@nvidia.com>
Signed-off-by: Colin Cross <ccross@android.com>

9 files changed, 2218 insertions, 56 deletions

diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index d801a9d47767..c034c73dfd71 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -6,15 +6,21 @@ obj-y                                   += clock.o
 obj-y                                   += timer.o
 obj-y                                   += pinmux.o
 obj-y                                   += powergate.o
+obj-$(CONFIG_PM_SLEEP)			+= pm.o
 obj-$(CONFIG_PM_SLEEP)			+= pm-irq.o
+obj-$(CONFIG_PM_SLEEP)			+= sleep.o
 obj-y					+= fuse.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += clock.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_clocks.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= tegra2_emc.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= wakeups-t2.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += pm-t2.o
+
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= pinmux-t2-tables.o
-obj-$(CONFIG_SMP)                       += platsmp.o localtimer.o headsmp.o
-obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
+obj-$(CONFIG_LOCAL_TIMERS)		+= localtimer.o
+obj-$(CONFIG_SMP)			+= platsmp.o
+obj-$(CONFIG_HOTPLUG_CPU)		+= hotplug.o
+obj-$(CONFIG_SMP)			+= headsmp.o
 obj-$(CONFIG_TEGRA_SYSTEM_DMA)		+= dma.o
 obj-$(CONFIG_CPU_FREQ)                  += cpu-tegra.o
 obj-$(CONFIG_TEGRA_PCI)			+= pcie.o
diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h
index 1d14df7eb7de..db46d4d279ba 100644
--- a/arch/arm/mach-tegra/board.h
+++ b/arch/arm/mach-tegra/board.h
@@ -29,7 +29,12 @@ void __init tegra_init_early(void);
 void __init tegra_map_common_io(void);
 void __init tegra_init_irq(void);
 void __init tegra_init_clock(void);
+void __init tegra_reserve(void);
 int __init tegra_pcie_init(bool init_port0, bool init_port1);
+void tegra_init_cache(void);
+
+extern unsigned long tegra_lp0_vec_start;
+extern unsigned long tegra_lp0_vec_size;
 
 extern struct sys_timer tegra_timer;
 #endif
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index c34a6ffde801..87ef402f912c 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -21,6 +21,7 @@
 #include <linux/io.h>
 #include <linux/clk.h>
 #include <linux/delay.h>
+#include <linux/memblock.h>
 
 #include <asm/hardware/cache-l2x0.h>
 
@@ -32,6 +33,10 @@
 #include "board.h"
 #include "clock.h"
 #include "fuse.h"
+#include "pm.h"
+
+unsigned long tegra_lp0_vec_start;
+unsigned long tegra_lp0_vec_size;
 
 void (*arch_reset)(char mode, const char *cmd) = tegra_assert_system_reset;
 
@@ -63,7 +68,7 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
 	{ NULL,		NULL,		0,		0},
 };
 
-void __init tegra_init_cache(void)
+void tegra_init_cache(void)
 {
 #ifdef CONFIG_CACHE_L2X0
 	void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
@@ -85,3 +90,28 @@ void __init tegra_init_early(void)
 	tegra_clk_init_from_table(common_clk_init_table);
 	tegra_init_cache();
 }
+
+static int __init tegra_lp0_vec_arg(char *options)
+{
+	char *p = options;
+
+	tegra_lp0_vec_size = memparse(p, &p);
+	if (*p == '@')
+		tegra_lp0_vec_start = memparse(p+1, &p);
+
+	return 0;
+}
+early_param("lp0_vec", tegra_lp0_vec_arg);
+
+void __init tegra_reserve(void)
+{
+	if (tegra_lp0_vec_size)
+		if (memblock_reserve(tegra_lp0_vec_start, tegra_lp0_vec_size))
+			pr_err("Failed to reserve lp0_vec %08lx@%08lx\n",
+				tegra_lp0_vec_size, tegra_lp0_vec_start);
+
+	pr_info("Tegra reserved memory:\n"
+		"LP0:                    %08lx - %08lx\n",
+		tegra_lp0_vec_start,
+		tegra_lp0_vec_start + tegra_lp0_vec_size - 1);
+}
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
index b5349b2f13d2..c055e21b375e 100644
--- a/arch/arm/mach-tegra/headsmp.S
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -1,61 +1,122 @@
+/*
+ * arch/arm/mach-tegra/headsmp.S
+ *
+ * SMP initialization routines for Tegra SoCs
+ *
+ * Copyright (c) 2009-2010, NVIDIA Corporation.
+ * Copyright (c) 2011 Google, Inc.
+ * Author: Colin Cross <ccross@android.com>
+ *         Gary King <gking@nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
 #include <linux/linkage.h>
 #include <linux/init.h>
 
-        .section ".text.head", "ax"
-	__CPUINIT
+#include <asm/assembler.h>
+#include <asm/cache.h>
 
+#include <mach/iomap.h>
+
+#ifdef CONFIG_SMP
 /*
- * Tegra specific entry point for secondary CPUs.
- *   The secondary kernel init calls v7_flush_dcache_all before it enables
- *   the L1; however, the L1 comes out of reset in an undefined state, so
- *   the clean + invalidate performed by v7_flush_dcache_all causes a bunch
- *   of cache lines with uninitialized data and uninitialized tags to get
- *   written out to memory, which does really unpleasant things to the main
- *   processor.  We fix this by performing an invalidate, rather than a
- *   clean + invalidate, before jumping into the kernel.
+ *	tegra_secondary_startup
+ *
+ *	 Initial secondary processor boot vector; jumps to kernel's
+ *	 secondary_startup routine
  */
-ENTRY(v7_invalidate_l1)
-        mov     r0, #0
-        mcr     p15, 2, r0, c0, c0, 0
-        mrc     p15, 1, r0, c0, c0, 0
-
-        ldr     r1, =0x7fff
-        and     r2, r1, r0, lsr #13
-
-        ldr     r1, =0x3ff
-
-        and     r3, r1, r0, lsr #3  @ NumWays - 1
-        add     r2, r2, #1          @ NumSets
-
-        and     r0, r0, #0x7
-        add     r0, r0, #4          @ SetShift
-
-        clz     r1, r3              @ WayShift
-        add     r4, r3, #1          @ NumWays
-1:      sub     r2, r2, #1          @ NumSets--
-        mov     r3, r4              @ Temp = NumWays
-2:      subs    r3, r3, #1          @ Temp--
-        mov     r5, r3, lsl r1
-        mov     r6, r2, lsl r0
-        orr     r5, r5, r6          @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
-        mcr     p15, 0, r5, c7, c6, 2
-        bgt     2b
-        cmp     r2, #0
-        bgt     1b
-        dsb
-        isb
-        mov     pc, lr
-ENDPROC(v7_invalidate_l1)
-
 ENTRY(tegra_secondary_startup)
-	msr	cpsr_fsxc, #0xd3
-        bl      v7_invalidate_l1
-	mrc	p15, 0, r0, c0, c0, 5
-        and	r0, r0, #15
-        ldr     r1, =0x6000f100
-        str     r0, [r1]
-1:      ldr     r2, [r1]
-        cmp     r0, r2
-        beq     1b
-        b       secondary_startup
+	bl	tegra_invalidate_l1
+	bl	tegra_enable_coresite
+	b	secondary_startup
 ENDPROC(tegra_secondary_startup)
+
+#ifdef CONFIG_PM
+/*
+ *	tegra_secondary_resume
+ *
+ *	  Secondary CPU boot vector when restarting a CPU following lp2 idle.
+ */
+ENTRY(tegra_secondary_resume)
+	bl	tegra_invalidate_l1
+	bl	tegra_enable_coresite
+	b	cpu_resume
+ENDPROC(tegra_secondary_resume)
+#endif
+#endif
+
+#ifdef CONFIG_PM
+/*
+ *	tegra_resume
+ *
+ *	  CPU boot vector when restarting the master CPU following
+ *	  an LP2 transition. Also branched to by LP0 and LP1 resume after
+ *	  re-enabling sdram.
+ */
+ENTRY(tegra_resume)
+	bl	tegra_invalidate_l1
+	bl	tegra_enable_coresite
+
+	/* enable SCU */
+	ldr	r0, =TEGRA_ARM_PERIF_BASE
+	ldr	r1, [r0]
+	orr	r1, r1, #1
+	str	r1, [r0]
+
+	b	cpu_resume
+ENDPROC(tegra_resume)
+#endif
+
+/*
+ *	tegra_invalidate_l1
+ *
+ *	  Invalidates the L1 data cache (no clean) during initial boot of a cpu
+ *
+ *	  Corrupted registers: r0-r6
+ */
+tegra_invalidate_l1:
+	mov	r0, #0
+	mcr	p15, 2, r0, c0, c0, 0
+	mrc	p15, 1, r0, c0, c0, 0
+
+	movw	r1, #0x7fff
+	and	r2, r1, r0, lsr #13
+
+	movw	r1, #0x3ff
+
+	and	r3, r1, r0, lsr #3	@ NumWays - 1
+	add	r2, r2, #1	@ NumSets
+
+	and	r0, r0, #0x7
+	add	r0, r0, #4	@ SetShift
+
+	clz	r1, r3		@ WayShift
+	add	r4, r3, #1	@ NumWays
+1:	sub	r2, r2, #1	@ NumSets--
+	mov	r3, r4		@ Temp = NumWays
+2:	subs	r3, r3, #1	@ Temp--
+	mov	r5, r3, lsl r1
+	mov	r6, r2, lsl r0
+	orr	r5, r5, r6	@ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
+	mcr	p15, 0, r5, c7, c6, 2
+	bgt	2b
+	cmp	r2, #0
+	bgt	1b
+	dsb
+	isb
+	mov	pc, lr
+
+	/* Enable Coresight access on cpu */
+tegra_enable_coresite:
+	ldr	r0, =0xC5ACCE55
+	mcr	p14, 0, r0, c7, c12, 6
+	mov	pc, lr
diff --git a/arch/arm/mach-tegra/pm-t2.c b/arch/arm/mach-tegra/pm-t2.c
new file mode 100644
index 000000000000..6cb70ca822fb
--- /dev/null
+++ b/arch/arm/mach-tegra/pm-t2.c
@@ -0,0 +1,356 @@
+/*
+ * arch/arm/mach-tegra/suspend-t2.c
+ *
+ * BootROM LP0 scratch register preservation for Tegra 2
+ *
+ * Copyright (c) 2009-2010, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <linux/init.h>
+#include <linux/io.h>
+
+#include <mach/iomap.h>
+#include <mach/irqs.h>
+
+#include "gpio-names.h"
+
+#define PMC_SCRATCH3	0x5c
+#define PMC_SCRATCH5	0x64
+#define PMC_SCRATCH6	0x68
+#define PMC_SCRATCH7	0x6c
+#define PMC_SCRATCH8	0x70
+#define PMC_SCRATCH9	0x74
+#define PMC_SCRATCH10	0x78
+#define PMC_SCRATCH11	0x7c
+#define PMC_SCRATCH12	0x80
+#define PMC_SCRATCH13	0x84
+#define PMC_SCRATCH14	0x88
+#define PMC_SCRATCH15	0x8c
+#define PMC_SCRATCH16	0x90
+#define PMC_SCRATCH17	0x94
+#define PMC_SCRATCH18	0x98
+#define PMC_SCRATCH19	0x9c
+#define PMC_SCRATCH20	0xa0
+#define PMC_SCRATCH21	0xa4
+#define PMC_SCRATCH22	0xa8
+#define PMC_SCRATCH23	0xac
+#define PMC_SCRATCH25	0x100
+#define PMC_SCRATCH35	0x128
+#define PMC_SCRATCH36	0x12c
+#define PMC_SCRATCH40	0x13c
+
+struct pmc_scratch_field {
+	unsigned long addr;
+	unsigned int mask;
+	int shift_src;
+	int shift_dst;
+};
+
+#define field(reg, start, end, dst)					\
+	{								\
+		.addr = (reg),						\
+		.mask = 0xfffffffful >> (31 - ((end) - (start))),	\
+		.shift_src = (start),					\
+		.shift_dst = (dst),					\
+	}
+
+static const struct pmc_scratch_field pllx[] __initdata = {
+	field(TEGRA_CLK_RESET_BASE + 0xe0, 20, 22, 15), /* PLLX_DIVP */
+	field(TEGRA_CLK_RESET_BASE + 0xe0, 8, 17, 5), /* PLLX_DIVN */
+	field(TEGRA_CLK_RESET_BASE + 0xe0, 0, 4, 0), /* PLLX_DIVM */
+	field(TEGRA_CLK_RESET_BASE + 0xe4, 8, 11, 22), /* PLLX_CPCON */
+	field(TEGRA_CLK_RESET_BASE + 0xe4, 4, 7, 18), /* PLLX_LFCON */
+	field(TEGRA_APB_MISC_BASE + 0x8e4, 24, 27, 27), /* XM2CFGC_VREF_DQ */
+	field(TEGRA_APB_MISC_BASE + 0x8c8, 3, 3, 26), /* XM2CFGC_SCHMT_EN */
+	field(TEGRA_APB_MISC_BASE + 0x8d0, 2, 2, 31), /* XM2CLKCFG_PREEMP_EN */
+};
+
+static const struct pmc_scratch_field emc_0[] __initdata = {
+	field(TEGRA_EMC_BASE + 0x3c, 0, 4, 27), /* R2W */
+	field(TEGRA_EMC_BASE + 0x34, 0, 5, 15), /* RAS */
+	field(TEGRA_EMC_BASE + 0x2c, 0, 5, 0), /* RC */
+	field(TEGRA_EMC_BASE + 0x30, 0, 8, 6), /* RFC */
+	field(TEGRA_EMC_BASE + 0x38, 0, 5, 21), /* RP */
+};
+
+static const struct pmc_scratch_field emc_1[] __initdata = {
+	field(TEGRA_EMC_BASE + 0x44, 0, 4, 5), /* R2P */
+	field(TEGRA_EMC_BASE + 0x4c, 0, 5, 15), /* RD_RCD */
+	field(TEGRA_EMC_BASE + 0x54, 0, 3, 27), /* RRD */
+	field(TEGRA_EMC_BASE + 0x48, 0, 4, 10), /* W2P */
+	field(TEGRA_EMC_BASE + 0x40, 0, 4, 0), /* W2R */
+	field(TEGRA_EMC_BASE + 0x50, 0, 5, 21), /* WR_RCD */
+};
+
+static const struct pmc_scratch_field emc_2[] __initdata = {
+	field(TEGRA_EMC_BASE + 0x2b8, 2, 2, 31), /* CLKCHANGE_SR_ENABLE */
+	field(TEGRA_EMC_BASE + 0x2b8, 10, 10, 30), /* USE_ADDR_CLK */
+	field(TEGRA_EMC_BASE + 0x80, 0, 4, 25), /* PCHG2PDEN */
+	field(TEGRA_EMC_BASE + 0x64, 0, 3, 12), /* QRST */
+	field(TEGRA_EMC_BASE + 0x68, 0, 3, 16), /* QSAFE */
+	field(TEGRA_EMC_BASE + 0x60, 0, 3, 8), /* QUSE */
+	field(TEGRA_EMC_BASE + 0x6c, 0, 4, 20), /* RDV */
+	field(TEGRA_EMC_BASE + 0x58, 0, 3, 0), /* REXT */
+	field(TEGRA_EMC_BASE + 0x5c, 0, 3, 4), /* WDV */
+};
+
+static const struct pmc_scratch_field emc_3[] __initdata = {
+	field(TEGRA_EMC_BASE + 0x74, 0, 3, 16), /* BURST_REFRESH_NUM */
+	field(TEGRA_EMC_BASE + 0x7c, 0, 3, 24), /* PDEX2RD */
+	field(TEGRA_EMC_BASE + 0x78, 0, 3, 20), /* PDEX2WR */
+	field(TEGRA_EMC_BASE + 0x70, 0, 4, 0), /* REFRESH_LO */
+	field(TEGRA_EMC_BASE + 0x70, 5, 15, 5), /* REFRESH */
+	field(TEGRA_EMC_BASE + 0xa0, 0, 3, 28), /* TCLKSTABLE */
+};
+
+static const struct pmc_scratch_field emc_4[] __initdata = {
+	field(TEGRA_EMC_BASE + 0x84, 0, 4, 0), /* ACT2PDEN */
+	field(TEGRA_EMC_BASE + 0x88, 0, 4, 5), /* AR2PDEN */
+	field(TEGRA_EMC_BASE + 0x8c, 0, 5, 10), /* RW2PDEN */
+	field(TEGRA_EMC_BASE + 0x94, 0, 3, 28), /* TCKE */
+	field(TEGRA_EMC_BASE + 0x90, 0, 11, 16), /* TXSR */
+};
+
+static const struct pmc_scratch_field emc_5[] __initdata = {
+	field(TEGRA_EMC_BASE + 0x8, 10, 10, 30), /* AP_REQ_BUSY_CTRL */
+	field(TEGRA_EMC_BASE + 0x8, 24, 24, 31), /* CFG_PRIORITY */
+	field(TEGRA_EMC_BASE + 0x8, 2, 2, 26), /* FORCE_UPDATE */
+	field(TEGRA_EMC_BASE + 0x8, 4, 4, 27), /* MRS_WAIT */
+	field(TEGRA_EMC_BASE + 0x8, 5, 5, 28), /* PERIODIC_QRST */
+	field(TEGRA_EMC_BASE + 0x8, 9, 9, 29), /* READ_DQM_CTRL */
+	field(TEGRA_EMC_BASE + 0x8, 0, 0, 24), /* READ_MUX */
+	field(TEGRA_EMC_BASE + 0x8, 1, 1, 25), /* WRITE_MUX */
+	field(TEGRA_EMC_BASE + 0xa4, 0, 3, 6), /* TCLKSTOP */
+	field(TEGRA_EMC_BASE + 0xa8, 0, 13, 10), /* TREFBW */
+	field(TEGRA_EMC_BASE + 0x9c, 0, 5, 0), /* TRPAB */
+};
+
+static const struct pmc_scratch_field emc_6[] __initdata = {
+	field(TEGRA_EMC_BASE + 0xfc, 0, 1, 0), /* DQSIB_DLY_MSB_BYTE_0 */
+	field(TEGRA_EMC_BASE + 0xfc, 8, 9, 2), /* DQSIB_DLY_MSB_BYTE_1 */
+	field(TEGRA_EMC_BASE + 0xfc, 16, 17, 4), /* DQSIB_DLY_MSB_BYTE_2 */
+	field(TEGRA_EMC_BASE + 0xfc, 24, 25, 6), /* DQSIB_DLY_MSB_BYTE_3 */
+	field(TEGRA_EMC_BASE + 0x110, 0, 1, 8), /* QUSE_DLY_MSB_BYTE_0 */
+	field(TEGRA_EMC_BASE + 0x110, 8, 9, 10), /* QUSE_DLY_MSB_BYTE_1 */
+	field(TEGRA_EMC_BASE + 0x110, 16, 17, 12), /* QUSE_DLY_MSB_BYTE_2 */
+	field(TEGRA_EMC_BASE + 0x110, 24, 25, 14), /* QUSE_DLY_MSB_BYTE_3 */
+	field(TEGRA_EMC_BASE + 0xac, 0, 3, 22), /* QUSE_EXTRA */
+	field(TEGRA_EMC_BASE + 0x98, 0, 5, 16), /* TFAW */
+	field(TEGRA_APB_MISC_BASE + 0x8e4, 5, 5, 30), /* XM2CFGC_VREF_DQ_EN */
+	field(TEGRA_APB_MISC_BASE + 0x8e4, 16, 19, 26), /* XM2CFGC_VREF_DQS */
+};
+
+static const struct pmc_scratch_field emc_dqsib_dly[] __initdata = {
+	field(TEGRA_EMC_BASE + 0xf8, 0, 31, 0), /* DQSIB_DLY_BYTE_0 - DQSIB_DLY_BYTE_3*/
+};
+
+static const struct pmc_scratch_field emc_quse_dly[] __initdata = {
+	field(TEGRA_EMC_BASE + 0x10c, 0, 31, 0), /* QUSE_DLY_BYTE_0 - QUSE_DLY_BYTE_3*/
+};
+
+static const struct pmc_scratch_field emc_clktrim[] __initdata = {
+	field(TEGRA_EMC_BASE + 0x2d0, 0, 29, 0), /* DATA0_CLKTRIM - DATA3_CLKTRIM +
+					* MCLK_ADDR_CLKTRIM */
+};
+
+static const struct pmc_scratch_field emc_autocal_fbio[] __initdata = {
+	field(TEGRA_EMC_BASE + 0x2a4, 29, 29, 29), /* AUTO_CAL_ENABLE */
+	field(TEGRA_EMC_BASE + 0x2a4, 30, 30, 30), /* AUTO_CAL_OVERRIDE */
+	field(TEGRA_EMC_BASE + 0x2a4, 8, 12, 14), /* AUTO_CAL_PD_OFFSET */
+	field(TEGRA_EMC_BASE + 0x2a4, 0, 4, 9), /* AUTO_CAL_PU_OFFSET */
+	field(TEGRA_EMC_BASE + 0x2a4, 16, 25, 19), /* AUTO_CAL_STEP */
+	field(TEGRA_EMC_BASE + 0xf4, 16, 16, 0), /* CFG_DEN_EARLY */
+	field(TEGRA_EMC_BASE + 0x104, 8, 8, 8), /* CTT_TERMINATION */
+	field(TEGRA_EMC_BASE + 0x104, 7, 7, 7), /* DIFFERENTIAL_DQS */
+	field(TEGRA_EMC_BASE + 0x104, 9, 9, 31), /* DQS_PULLD */
+	field(TEGRA_EMC_BASE + 0x104, 0, 1, 4), /* DRAM_TYPE */
+	field(TEGRA_EMC_BASE + 0x104, 4, 4, 6), /* DRAM_WIDTH */
+	field(TEGRA_EMC_BASE + 0x114, 0, 2, 1), /* CFG_QUSE_LATE */
+};
+
+static const struct pmc_scratch_field emc_autocal_interval[] __initdata = {
+	field(TEGRA_EMC_BASE + 0x2a8, 0, 27, 0), /* AUTOCAL_INTERVAL */
+	field(TEGRA_EMC_BASE + 0x2b8, 1, 1, 29), /* CLKCHANGE_PD_ENABLE */
+	field(TEGRA_EMC_BASE + 0x2b8, 0, 0, 28), /* CLKCHANGE_REQ_ENABLE */
+	field(TEGRA_EMC_BASE + 0x2b8, 8, 9, 30), /* PIN_CONFIG */
+};
+
+static const struct pmc_scratch_field emc_cfgs[] __initdata = {
+	field(TEGRA_EMC_BASE + 0x10, 8, 9, 3), /* EMEM_BANKWIDTH */
+	field(TEGRA_EMC_BASE + 0x10, 0, 2, 0), /* EMEM_COLWIDTH */
+	field(TEGRA_EMC_BASE + 0x10, 16, 19, 5), /* EMEM_DEVSIZE */
+	field(TEGRA_EMC_BASE + 0x10, 24, 25, 9), /* EMEM_NUMDEV */
+	field(TEGRA_EMC_BASE + 0xc, 24, 24, 21), /* AUTO_PRE_RD */
+	field(TEGRA_EMC_BASE + 0xc, 25, 25, 22), /* AUTO_PRE_WR */
+	field(TEGRA_EMC_BASE + 0xc, 16, 16, 20), /* CLEAR_AP_PREV_SPREQ */
+	field(TEGRA_EMC_BASE + 0xc, 29, 29, 23), /* DRAM_ACPD */
+	field(TEGRA_EMC_BASE + 0xc, 30, 30, 24), /* DRAM_CLKSTOP_PDSR_ONLY */
+	field(TEGRA_EMC_BASE + 0xc, 31, 31, 25), /* DRAM_CLKSTOP */
+	field(TEGRA_EMC_BASE + 0xc, 8, 15, 12), /* PRE_IDLE_CYCLES */
+	field(TEGRA_EMC_BASE + 0xc, 0, 0, 11), /* PRE_IDLE_EN */
+	field(TEGRA_EMC_BASE + 0x2bc, 28, 29, 28), /* CFG_DLL_LOCK_LIMIT */
+	field(TEGRA_EMC_BASE + 0x2bc, 6, 7, 30), /* CFG_DLL_MODE */
+	field(TEGRA_MC_BASE + 0x10c, 0, 0, 26), /* LL_CTRL */
+	field(TEGRA_MC_BASE + 0x10c, 1, 1, 27), /* LL_SEND_BOTH */
+};
+
+static const struct pmc_scratch_field emc_adr_cfg1[] __initdata = {
+	field(TEGRA_EMC_BASE + 0x14, 8, 9, 8), /* EMEM1_BANKWIDTH */
+	field(TEGRA_EMC_BASE + 0x14, 0, 2, 5), /* EMEM1_COLWIDTH */
+	field(TEGRA_EMC_BASE + 0x14, 16, 19, 10), /* EMEM1_DEVSIZE */
+	field(TEGRA_EMC_BASE + 0x2dc, 24, 28, 0), /* TERM_DRVUP */
+	field(TEGRA_APB_MISC_BASE + 0x8d4, 0, 3, 14), /* XM2COMP_VREF_SEL */
+	field(TEGRA_APB_MISC_BASE + 0x8d8, 16, 18, 21), /* XM2VTTGEN_CAL_DRVDN */
+	field(TEGRA_APB_MISC_BASE + 0x8d8, 24, 26, 18), /* XM2VTTGEN_CAL_DRVUP */
+	field(TEGRA_APB_MISC_BASE + 0x8d8, 1, 1, 30), /* XM2VTTGEN_SHORT_PWRGND */
+	field(TEGRA_APB_MISC_BASE + 0x8d8, 0, 0, 31), /* XM2VTTGEN_SHORT */
+	field(TEGRA_APB_MISC_BASE + 0x8d8, 12, 14, 24), /* XM2VTTGEN_VAUXP_LEVEL */
+	field(TEGRA_APB_MISC_BASE + 0x8d8, 8, 10, 27), /* XM2VTTGEN_VCLAMP_LEVEL */
+};
+
+static const struct pmc_scratch_field emc_digital_dll[] __initdata = {
+	field(TEGRA_EMC_BASE + 0x2bc, 1, 1, 23), /* DLI_TRIMMER_EN */
+	field(TEGRA_EMC_BASE + 0x2bc, 0, 0, 22), /* DLL_EN */
+	field(TEGRA_EMC_BASE + 0x2bc, 5, 5, 27), /* DLL_LOWSPEED */
+	field(TEGRA_EMC_BASE + 0x2bc, 2, 2, 24), /* DLL_OVERRIDE_EN */
+	field(TEGRA_EMC_BASE + 0x2bc, 8, 11, 28), /* DLL_UDSET */
+	field(TEGRA_EMC_BASE + 0x2bc, 4, 4, 26), /* PERBYTE_TRIMMER_OVERRIDE */
+	field(TEGRA_EMC_BASE + 0x2bc, 3, 3, 25), /* USE_SINGLE_DLL */
+	field(TEGRA_MC_BASE + 0xc, 0, 21, 0), /* EMEM_SIZE_KB */
+};
+
+static const struct pmc_scratch_field emc_dqs_clktrim[] __initdata = {
+	field(TEGRA_EMC_BASE + 0x2d4, 0, 29, 0), /* DQS0_CLKTRIM - DQS3 + MCLK*/
+	field(TEGRA_APB_MISC_BASE + 0x8e4, 3, 3, 31), /* XM2CFGC_CTT_HIZ_EN */
+	field(TEGRA_APB_MISC_BASE + 0x8e4, 4, 4, 30), /* XM2CFGC_VREF_DQS_EN */
+};
+
+static const struct pmc_scratch_field emc_dq_clktrim[] __initdata = {
+	field(TEGRA_EMC_BASE + 0x2d8, 0, 29, 0),
+	field(TEGRA_APB_MISC_BASE + 0x8e4, 2, 2, 30), /* XM2CFGC_PREEMP_EN */
+	field(TEGRA_APB_MISC_BASE + 0x8e4, 0, 0, 31), /* XM2CFGC_RX_FT_REC_EN */
+};
+
+static const struct pmc_scratch_field emc_dll_xform_dqs[] __initdata = {
+	field(TEGRA_EMC_BASE + 0x2bc, 16, 25, 20), /* CFG_DLL_OVERRIDE_VAL */
+	field(TEGRA_EMC_BASE + 0x2c0, 0, 4, 0), /* DQS_MULT */
+	field(TEGRA_EMC_BASE + 0x2c0, 8, 22, 5), /* DQS_OFFS */
+	field(TEGRA_MC_BASE + 0x10c, 31, 31, 30), /* LL_DRAM_INTERLEAVE */
+};
+
+static const struct pmc_scratch_field emc_odt_rw[] __initdata = {
+	field(TEGRA_EMC_BASE + 0x2c4, 0, 4, 0), /* QUSE_MULT */
+	field(TEGRA_EMC_BASE + 0x2c4, 8, 22, 5), /* QUSE_OFF */
+	field(TEGRA_EMC_BASE + 0xb4, 31, 31, 29), /* DISABLE_ODT_DURING_READ */
+	field(TEGRA_EMC_BASE + 0xb4, 30, 30, 28), /* B4_READ */
+	field(TEGRA_EMC_BASE + 0xb4, 0, 2, 25), /* RD_DELAY */
+	field(TEGRA_EMC_BASE + 0xb0, 31, 31, 24), /* ENABLE_ODT_DURING_WRITE */
+	field(TEGRA_EMC_BASE + 0xb0, 30, 30, 23), /* B4_WRITE */
+	field(TEGRA_EMC_BASE + 0xb0, 0, 2, 20), /* WR_DELAY */
+};
+
+static const struct pmc_scratch_field arbitration_xbar[] __initdata = {
+	field(TEGRA_AHB_GIZMO_BASE + 0xdc, 0, 31, 0),
+};
+
+static const struct pmc_scratch_field emc_zcal[] __initdata = {
+	field(TEGRA_EMC_BASE + 0x2e0, 0, 23, 0), /* ZCAL_REF_INTERVAL */
+	field(TEGRA_EMC_BASE + 0x2e4, 0, 7, 24), /* ZCAL_WAIT_CNT */
+};
+
+static const struct pmc_scratch_field emc_ctt_term[] __initdata = {
+	field(TEGRA_EMC_BASE + 0x2dc, 15, 19, 26), /* TERM_DRVDN */
+	field(TEGRA_EMC_BASE + 0x2dc, 8, 12, 21), /* TERM_OFFSET */
+	field(TEGRA_EMC_BASE + 0x2dc, 31, 31, 31), /* TERM_OVERRIDE */
+	field(TEGRA_EMC_BASE + 0x2dc, 0, 2, 18), /* TERM_SLOPE */
+	field(TEGRA_EMC_BASE + 0x2e8, 16, 23, 8), /* ZQ_MRW_MA */
+	field(TEGRA_EMC_BASE + 0x2e8, 0, 7, 0), /* ZQ_MRW_OP */
+};
+
+static const struct pmc_scratch_field xm2_cfgd[] __initdata = {
+	field(TEGRA_APB_MISC_BASE + 0x8e8, 16, 18, 9), /* CFGD0_DLYIN_TRM */
+	field(TEGRA_APB_MISC_BASE + 0x8e8, 20, 22, 6), /* CFGD1_DLYIN_TRM */
+	field(TEGRA_APB_MISC_BASE + 0x8e8, 24, 26, 3), /* CFGD2_DLYIN_TRM */
+	field(TEGRA_APB_MISC_BASE + 0x8e8, 28, 30, 0), /* CFGD3_DLYIN_TRM */
+	field(TEGRA_APB_MISC_BASE + 0x8e8, 3, 3, 12), /* XM2CFGD_CTT_HIZ_EN */
+	field(TEGRA_APB_MISC_BASE + 0x8e8, 2, 2, 13), /* XM2CFGD_PREEMP_EN */
+	field(TEGRA_APB_MISC_BASE + 0x8e8, 0, 0, 14), /* CM2CFGD_RX_FT_REC_EN */
+};
+
+struct pmc_scratch_reg {
+	const struct pmc_scratch_field *fields;
+	void __iomem *scratch_addr;
+	int num_fields;
+};
+
+#define scratch(offs, field_list)					\
+	{								\
+		.scratch_addr = IO_ADDRESS(TEGRA_PMC_BASE) + offs,	\
+		.fields = field_list,					\
+		.num_fields = ARRAY_SIZE(field_list),			\
+	}
+
+static const struct pmc_scratch_reg scratch[] __initdata = {
+	scratch(PMC_SCRATCH3, pllx),
+	scratch(PMC_SCRATCH5, emc_0),
+	scratch(PMC_SCRATCH6, emc_1),
+	scratch(PMC_SCRATCH7, emc_2),
+	scratch(PMC_SCRATCH8, emc_3),
+	scratch(PMC_SCRATCH9, emc_4),
+	scratch(PMC_SCRATCH10, emc_5),
+	scratch(PMC_SCRATCH11, emc_6),
+	scratch(PMC_SCRATCH12, emc_dqsib_dly),
+	scratch(PMC_SCRATCH13, emc_quse_dly),
+	scratch(PMC_SCRATCH14, emc_clktrim),
+	scratch(PMC_SCRATCH15, emc_autocal_fbio),
+	scratch(PMC_SCRATCH16, emc_autocal_interval),
+	scratch(PMC_SCRATCH17, emc_cfgs),
+	scratch(PMC_SCRATCH18, emc_adr_cfg1),
+	scratch(PMC_SCRATCH19, emc_digital_dll),
+	scratch(PMC_SCRATCH20, emc_dqs_clktrim),
+	scratch(PMC_SCRATCH21, emc_dq_clktrim),
+	scratch(PMC_SCRATCH22, emc_dll_xform_dqs),
+	scratch(PMC_SCRATCH23, emc_odt_rw),
+	scratch(PMC_SCRATCH25, arbitration_xbar),
+	scratch(PMC_SCRATCH35, emc_zcal),
+	scratch(PMC_SCRATCH36, emc_ctt_term),
+	scratch(PMC_SCRATCH40, xm2_cfgd),
+};
+
+void __init tegra2_lp0_suspend_init(void)
+{
+	int i;
+	int j;
+	unsigned int v;
+	unsigned int r;
+
+	for (i = 0; i < ARRAY_SIZE(scratch); i++) {
+		r = 0;
+
+		for (j = 0; j < scratch[i].num_fields; j++) {
+			v = readl(IO_ADDRESS(scratch[i].fields[j].addr));
+			v >>= scratch[i].fields[j].shift_src;
+			v &= scratch[i].fields[j].mask;
+			v <<= scratch[i].fields[j].shift_dst;
+			r |= v;
+		}
+
+		writel(r, scratch[i].scratch_addr);
+	}
+}
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
new file mode 100644
index 000000000000..9fc001950803
--- /dev/null
+++ b/arch/arm/mach-tegra/pm.c
@@ -0,0 +1,843 @@
+/*
+ * arch/arm/mach-tegra/suspend.c
+ *
+ * CPU complex suspend & resume functions for Tegra SoCs
+ *
+ * Copyright (c) 2009-2010, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/sched.h>
+#include <linux/smp.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/debugfs.h>
+#include <linux/delay.h>
+#include <linux/suspend.h>
+#include <linux/slab.h>
+#include <linux/serial_reg.h>
+#include <linux/seq_file.h>
+#include <linux/uaccess.h>
+#include <linux/syscore_ops.h>
+
+#include <asm/cacheflush.h>
+#include <asm/cpu_pm.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/hardware/gic.h>
+#include <asm/localtimer.h>
+#include <asm/pgalloc.h>
+#include <asm/tlbflush.h>
+
+#include <mach/iomap.h>
+#include <mach/irqs.h>
+
+#include "board.h"
+#include "pm.h"
+#include "pm-irq.h"
+#include "sleep.h"
+
+struct suspend_context {
+	/*
+	 * The next 7 values are referenced by offset in __restart_plls
+	 * in headsmp-t2.S, and should not be moved
+	 */
+	u32 pllx_misc;
+	u32 pllx_base;
+	u32 pllp_misc;
+	u32 pllp_base;
+	u32 pllp_outa;
+	u32 pllp_outb;
+	u32 pll_timeout;
+
+	u32 cpu_burst;
+	u32 clk_csite_src;
+	u32 cclk_divider;
+
+	u32 mc[3];
+	u8 uart[5];
+};
+
+static u8 *iram_save;
+static unsigned long iram_save_size;
+
+struct suspend_context tegra_sctx;
+
+static void __iomem *iram_code = IO_ADDRESS(TEGRA_IRAM_CODE_AREA);
+static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
+#ifdef CONFIG_PM
+static void __iomem *clk_rst = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
+static void __iomem *flow_ctrl = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE);
+static void __iomem *evp_reset =
+	IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100;
+#endif
+
+#define TEGRA_POWER_PWRREQ_POLARITY	(1 << 8)   /* core power request polarity */
+#define TEGRA_POWER_PWRREQ_OE		(1 << 9)   /* core power request enable */
+#define TEGRA_POWER_SYSCLK_POLARITY	(1 << 10)  /* sys clk polarity */
+#define TEGRA_POWER_SYSCLK_OE		(1 << 11)  /* system clock enable */
+#define TEGRA_POWER_PWRGATE_DIS		(1 << 12)  /* power gate disabled */
+#define TEGRA_POWER_EFFECT_LP0		(1 << 14)  /* enter LP0 when CPU pwr gated */
+#define TEGRA_POWER_CPU_PWRREQ_POLARITY (1 << 15)  /* CPU power request polarity */
+#define TEGRA_POWER_CPU_PWRREQ_OE	(1 << 16)  /* CPU power request enable */
+
+#define PMC_CTRL		0x0
+#define PMC_CTRL_LATCH_WAKEUPS	(1 << 5)
+#define PMC_WAKE_MASK		0xc
+#define PMC_WAKE_LEVEL		0x10
+#define PMC_DPAD_ORIDE		0x1C
+#define PMC_WAKE_DELAY		0xe0
+#define PMC_DPD_SAMPLE		0x20
+
+#define PMC_WAKE_STATUS		0x14
+#define PMC_SW_WAKE_STATUS	0x18
+#define PMC_COREPWRGOOD_TIMER	0x3c
+#define PMC_SCRATCH0		0x50
+#define PMC_SCRATCH1		0x54
+#define PMC_CPUPWRGOOD_TIMER	0xc8
+#define PMC_CPUPWROFF_TIMER	0xcc
+#define PMC_COREPWROFF_TIMER	PMC_WAKE_DELAY
+
+#define CLK_RESET_CCLK_BURST	0x20
+#define CLK_RESET_CCLK_DIVIDER  0x24
+#define CLK_RESET_PLLC_BASE	0x80
+#define CLK_RESET_PLLM_BASE	0x90
+#define CLK_RESET_PLLX_BASE	0xe0
+#define CLK_RESET_PLLX_MISC	0xe4
+#define CLK_RESET_PLLP_BASE	0xa0
+#define CLK_RESET_PLLP_OUTA	0xa4
+#define CLK_RESET_PLLP_OUTB	0xa8
+#define CLK_RESET_PLLP_MISC	0xac
+
+#define CLK_RESET_SOURCE_CSITE	0x1d4
+
+#define CLK_RESET_CCLK_BURST_POLICY_SHIFT 28
+#define CLK_RESET_CCLK_BURST_POLICY_PLLM   3
+#define CLK_RESET_CCLK_BURST_POLICY_PLLX   8
+
+#define FLOW_CTRL_CPU_CSR(cpu)	(0x8 + 0x10 * (cpu))
+#define FLOW_CTRL_HALT_CPU(cpu) ((cpu) == 0 ? 0x0 : (0x4 + cpu * 0x10))
+
+#define FLOW_CTRL_CSR_CLEAR_EVENT	(1 << 14)
+#define FLOW_CTRL_CSR_WFE_BITMAP	(3 << 4)
+#define FLOW_CTRL_CSR_WFE_CPU0		(1 << 4)
+#define FLOW_CTRL_CSR_ENABLE		(1 << 0)
+
+#define EMC_MRW_0		0x0e8
+#define EMC_MRW_DEV_SELECTN     30
+#define EMC_MRW_DEV_NONE	(3 << EMC_MRW_DEV_SELECTN)
+
+#define MC_SECURITY_START	0x6c
+#define MC_SECURITY_SIZE	0x70
+#define MC_SECURITY_CFG2	0x7c
+
+unsigned long tegra_pgd_phys;  /* pgd used by hotplug & LP2 bootup */
+static pgd_t *tegra_pgd;
+
+static int tegra_last_pclk;
+static struct clk *tegra_pclk;
+static const struct tegra_suspend_platform_data *pdata;
+static enum tegra_suspend_mode current_suspend_mode = TEGRA_SUSPEND_NONE;
+
+static DEFINE_SPINLOCK(tegra_lp2_lock);
+static cpumask_t tegra_in_lp2;
+
+unsigned long tegra_cpu_power_good_time(void)
+{
+	if (WARN_ON_ONCE(!pdata))
+		return 5000;
+
+	return pdata->cpu_timer;
+}
+
+unsigned long tegra_cpu_power_off_time(void)
+{
+	if (WARN_ON_ONCE(!pdata))
+		return 5000;
+
+	return pdata->cpu_off_timer;
+}
+
+/* ensures that sufficient time is passed for a register write to
+ * serialize into the 32KHz domain */
+static void pmc_32kwritel(u32 val, unsigned long offs)
+{
+	writel(val, pmc + offs);
+	udelay(130);
+}
+
+static void set_power_timers(unsigned long us_on, unsigned long us_off,
+			     long rate)
+{
+	unsigned long long ticks;
+	unsigned long long pclk;
+
+	if (WARN_ON_ONCE(rate <= 0))
+		pclk = 100000000;
+	else
+		pclk = rate;
+
+	if (rate != tegra_last_pclk) {
+		ticks = (us_on * pclk) + 999999ull;
+		do_div(ticks, 1000000);
+		writel((unsigned long)ticks, pmc + PMC_CPUPWRGOOD_TIMER);
+
+		ticks = (us_off * pclk) + 999999ull;
+		do_div(ticks, 1000000);
+		writel((unsigned long)ticks, pmc + PMC_CPUPWROFF_TIMER);
+		wmb();
+	}
+	tegra_last_pclk = pclk;
+}
+
+/*
+ * create_suspend_pgtable
+ *
+ * Creates a page table with identity mappings of physical memory and IRAM
+ * for use when the MMU is off, in addition to all the regular kernel mappings.
+ */
+static int create_suspend_pgtable(void)
+{
+	tegra_pgd = pgd_alloc(&init_mm);
+	if (!tegra_pgd)
+		return -ENOMEM;
+
+	identity_mapping_add(tegra_pgd, PLAT_PHYS_OFFSET, IO_IRAM_PHYS);
+	identity_mapping_add(tegra_pgd, IO_IRAM_PHYS,
+		IO_IRAM_PHYS + SECTION_SIZE);
+
+	tegra_pgd_phys = virt_to_phys(tegra_pgd);
+
+	return 0;
+}
+
+static int tegra_reset_sleeping_cpu(int cpu)
+{
+	int ret = 0;
+
+	BUG_ON(cpu == smp_processor_id());
+	tegra_pen_lock();
+
+	if (readl(pmc + PMC_SCRATCH41) == CPU_RESETTABLE)
+		tegra_cpu_reset(cpu);
+	else
+		ret = -EINVAL;
+
+	tegra_pen_unlock();
+
+	local_fiq_enable();
+
+	return ret;
+}
+
+static void tegra_wake_reset_cpu(int cpu)
+{
+	u32 reg;
+
+	writel(virt_to_phys(tegra_secondary_resume), evp_reset);
+
+	/* enable cpu clock on cpu */
+	reg = readl(clk_rst + 0x4c);
+	writel(reg & ~(1 << (8 + cpu)), clk_rst + 0x4c);
+
+	reg = 0x1111 << cpu;
+	writel(reg, clk_rst + 0x344);
+
+	/* unhalt the cpu */
+	writel(0, flow_ctrl + 0x14);
+}
+
+#ifdef CONFIG_PM
+/*
+ * restore_cpu_complex
+ *
+ * restores cpu clock setting, clears flow controller
+ *
+ * always called on cpu 0, even when suspend_cpu_complex was called on cpu 1
+ * in idle
+ */
+static void restore_cpu_complex(void)
+{
+	unsigned int reg;
+	int i;
+
+	/* restore original burst policy setting */
+
+	writel(tegra_sctx.pllx_misc, clk_rst + CLK_RESET_PLLX_MISC);
+	writel(tegra_sctx.pllx_base, clk_rst + CLK_RESET_PLLX_BASE);
+	writel(tegra_sctx.pllp_misc, clk_rst + CLK_RESET_PLLP_MISC);
+	writel(tegra_sctx.pllp_base, clk_rst + CLK_RESET_PLLP_BASE);
+	writel(tegra_sctx.pllp_outa, clk_rst + CLK_RESET_PLLP_OUTA);
+	writel(tegra_sctx.pllp_outb, clk_rst + CLK_RESET_PLLP_OUTB);
+	udelay(300);
+	writel(tegra_sctx.cclk_divider, clk_rst + CLK_RESET_CCLK_DIVIDER);
+	writel(tegra_sctx.cpu_burst, clk_rst + CLK_RESET_CCLK_BURST);
+	writel(tegra_sctx.clk_csite_src, clk_rst + CLK_RESET_SOURCE_CSITE);
+
+	/* do not power-gate the CPU when flow controlled */
+	for (i = 0; i < num_possible_cpus(); i++) {
+		reg = readl(flow_ctrl + FLOW_CTRL_CPU_CSR(i));
+		reg &= ~FLOW_CTRL_CSR_WFE_BITMAP;	/* clear wfe bitmap */
+		reg &= ~FLOW_CTRL_CSR_ENABLE;		/* clear enable */
+		reg |= FLOW_CTRL_CSR_CLEAR_EVENT;	/* clear event */
+		writel(reg, flow_ctrl + FLOW_CTRL_CPU_CSR(i));
+		wmb();
+	}
+}
+
+/*
+ * suspend_cpu_complex
+ *
+ * saves pll state for use by restart_plls, prepares flow controller for
+ * transition to suspend state
+ *
+ * in suspend, always called on cpu 0
+ * in idle, called on the last cpu to request lp2
+ */
+static void suspend_cpu_complex(void)
+{
+	unsigned int reg;
+	int i;
+	int cpu = smp_processor_id();
+
+	/* switch coresite to clk_m, save off original source */
+	tegra_sctx.clk_csite_src = readl(clk_rst + CLK_RESET_SOURCE_CSITE);
+	writel(3<<30, clk_rst + CLK_RESET_SOURCE_CSITE);
+
+	tegra_sctx.cpu_burst = readl(clk_rst + CLK_RESET_CCLK_BURST);
+	tegra_sctx.pllx_base = readl(clk_rst + CLK_RESET_PLLX_BASE);
+	tegra_sctx.pllx_misc = readl(clk_rst + CLK_RESET_PLLX_MISC);
+	tegra_sctx.pllp_base = readl(clk_rst + CLK_RESET_PLLP_BASE);
+	tegra_sctx.pllp_outa = readl(clk_rst + CLK_RESET_PLLP_OUTA);
+	tegra_sctx.pllp_outb = readl(clk_rst + CLK_RESET_PLLP_OUTB);
+	tegra_sctx.pllp_misc = readl(clk_rst + CLK_RESET_PLLP_MISC);
+	tegra_sctx.cclk_divider = readl(clk_rst + CLK_RESET_CCLK_DIVIDER);
+
+	reg = readl(flow_ctrl + FLOW_CTRL_CPU_CSR(cpu));
+	reg &= ~FLOW_CTRL_CSR_WFE_BITMAP;	/* clear wfe bitmap */
+	reg |= FLOW_CTRL_CSR_CLEAR_EVENT;	/* clear event flag */
+	reg |= FLOW_CTRL_CSR_WFE_CPU0 << cpu;	/* enable power gating on wfe */
+	reg |= FLOW_CTRL_CSR_ENABLE;		/* enable power gating */
+	writel(reg, flow_ctrl + FLOW_CTRL_CPU_CSR(cpu));
+	wmb();
+
+	for (i = 0; i < num_possible_cpus(); i++) {
+		if (i == cpu)
+			continue;
+		reg = readl(flow_ctrl + FLOW_CTRL_CPU_CSR(i));
+		reg |= FLOW_CTRL_CSR_CLEAR_EVENT;
+		writel(reg, flow_ctrl + FLOW_CTRL_CPU_CSR(i));
+		writel(0, flow_ctrl + FLOW_CTRL_HALT_CPU(i));
+		wmb();
+	}
+}
+
+int tegra_reset_other_cpus(int cpu)
+{
+	int i;
+	int abort = -1;
+
+	for_each_online_cpu(i) {
+		if (i != cpu) {
+			if (tegra_reset_sleeping_cpu(i)) {
+				abort = i;
+				break;
+			}
+		}
+	}
+
+	if (abort >= 0) {
+		for_each_online_cpu(i) {
+			if (i != cpu && i < abort)
+				tegra_wake_reset_cpu(i);
+		}
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+void tegra_idle_lp2_last(void)
+{
+	u32 reg;
+	int i;
+	int cpu = smp_processor_id();
+
+	while (tegra_cpu_is_resettable_soon())
+		cpu_relax();
+
+	if (tegra_reset_other_cpus(cpu))
+		return;
+
+	/* Only the last cpu down does the final suspend steps */
+	reg = readl(pmc + PMC_CTRL);
+	reg |= TEGRA_POWER_CPU_PWRREQ_OE;
+	reg |= TEGRA_POWER_PWRREQ_OE;
+	reg &= ~TEGRA_POWER_EFFECT_LP0;
+	pmc_32kwritel(reg, PMC_CTRL);
+
+	writel(virt_to_phys(tegra_resume), evp_reset);
+
+	set_power_timers(pdata->cpu_timer, pdata->cpu_off_timer,
+		clk_get_rate(tegra_pclk));
+
+	cpu_complex_pm_enter();
+
+	suspend_cpu_complex();
+	flush_cache_all();
+	outer_flush_all();
+	outer_disable();
+
+	tegra_sleep_cpu(PLAT_PHYS_OFFSET - PAGE_OFFSET);
+
+	l2x0_enable();
+	restore_cpu_complex();
+	cpu_complex_pm_exit();
+
+	spin_lock(&tegra_lp2_lock);
+
+	cpumask_clear_cpu(cpu, &tegra_in_lp2);
+
+	for_each_online_cpu(i) {
+		if (i != cpu) {
+			tegra_wake_reset_cpu(i);
+			cpumask_clear_cpu(i, &tegra_in_lp2);
+		}
+	}
+
+	spin_unlock(&tegra_lp2_lock);
+}
+
+void tegra_idle_lp2(void)
+{
+	bool last_cpu = false;
+	int cpu = smp_processor_id();
+
+	spin_lock(&tegra_lp2_lock);
+
+	cpumask_set_cpu(cpu, &tegra_in_lp2);
+	if (cpumask_equal(&tegra_in_lp2, cpu_online_mask))
+		last_cpu = true;
+	else
+		tegra_cpu_set_resettable_soon();
+
+	spin_unlock(&tegra_lp2_lock);
+
+	cpu_pm_enter();
+
+	local_fiq_disable();
+
+	if (last_cpu)
+		tegra_idle_lp2_last();
+	else
+		tegra_sleep_wfi(PLAT_PHYS_OFFSET - PAGE_OFFSET);
+
+	local_fiq_enable();
+
+	cpu_pm_exit();
+
+	spin_lock(&tegra_lp2_lock);
+	cpumask_clear_cpu(cpu, &tegra_in_lp2);
+	spin_unlock(&tegra_lp2_lock);
+}
+
+static int tegra_common_suspend(void)
+{
+	void __iomem *mc = IO_ADDRESS(TEGRA_MC_BASE);
+
+	tegra_sctx.mc[0] = readl(mc + MC_SECURITY_START);
+	tegra_sctx.mc[1] = readl(mc + MC_SECURITY_SIZE);
+	tegra_sctx.mc[2] = readl(mc + MC_SECURITY_CFG2);
+
+	/* copy the reset vector and SDRAM shutdown code into IRAM */
+	memcpy(iram_save, iram_code, iram_save_size);
+	memcpy(iram_code, &tegra_iram_start, iram_save_size);
+
+	return 0;
+}
+
+static void tegra_common_resume(void)
+{
+	void __iomem *mc = IO_ADDRESS(TEGRA_MC_BASE);
+	void __iomem *emc = IO_ADDRESS(TEGRA_EMC_BASE);
+
+	/* Clear DPD sample */
+	writel(0x0, pmc + PMC_DPD_SAMPLE);
+
+	writel(tegra_sctx.mc[0], mc + MC_SECURITY_START);
+	writel(tegra_sctx.mc[1], mc + MC_SECURITY_SIZE);
+	writel(tegra_sctx.mc[2], mc + MC_SECURITY_CFG2);
+
+	/* trigger emc mode write */
+	writel(EMC_MRW_DEV_NONE, emc + EMC_MRW_0);
+
+	/* clear scratch registers shared by suspend and the reset pen */
+	writel(0x0, pmc + PMC_SCRATCH39);
+	writel(0x0, pmc + PMC_SCRATCH41);
+
+	/* restore IRAM */
+	memcpy(iram_code, iram_save, iram_save_size);
+}
+
+static int tegra_suspend_prepare_late(void)
+{
+	disable_irq(INT_SYS_STATS_MON);
+	return 0;
+}
+
+static void tegra_suspend_wake(void)
+{
+	enable_irq(INT_SYS_STATS_MON);
+}
+
+static void tegra_pm_set(enum tegra_suspend_mode mode)
+{
+	u32 reg;
+	unsigned long rate = 32768;
+
+	reg = readl(pmc + PMC_CTRL);
+	reg |= TEGRA_POWER_CPU_PWRREQ_OE;
+	reg |= TEGRA_POWER_PWRREQ_OE;
+	reg &= ~TEGRA_POWER_EFFECT_LP0;
+
+	switch (mode) {
+	case TEGRA_SUSPEND_LP0:
+		/*
+		 * lp0 boots through the AVP, which then resumes the AVP to
+		 * the address in scratch 39, and the cpu to the address in
+		 * scratch 41 to tegra_resume
+		 */
+		writel(0x0, pmc + PMC_SCRATCH39);
+		writel(virt_to_phys(tegra_resume), pmc + PMC_SCRATCH41);
+		reg |= TEGRA_POWER_EFFECT_LP0;
+
+		/* Enable DPD sample to trigger sampling pads data and direction
+		 * in which pad will be driven during lp0 mode*/
+		writel(0x1, pmc + PMC_DPD_SAMPLE);
+		break;
+	case TEGRA_SUSPEND_LP1:
+		/*
+		 * lp1 boots through the normal cpu reset vector pointing to
+		 * tegra_lp1_reset in IRAM, which resumes the CPU to
+		 * the address in scratch 41 to tegra_resume
+		 */
+		writel(&tegra_lp1_reset - &tegra_iram_start +
+			TEGRA_IRAM_CODE_AREA, evp_reset);
+		writel(virt_to_phys(tegra_resume), pmc + PMC_SCRATCH41);
+		break;
+	case TEGRA_SUSPEND_LP2:
+		/*
+		 * lp2 boots through the normal cpu reset vector directly to
+		 * tegra_resume
+		 */
+		writel(virt_to_phys(tegra_resume), evp_reset);
+		rate = clk_get_rate(tegra_pclk);
+		break;
+	default:
+		BUG();
+	}
+
+	set_power_timers(pdata->cpu_timer, pdata->cpu_off_timer, rate);
+
+	pmc_32kwritel(reg, PMC_CTRL);
+
+	/* Set warmboot flag */
+	reg = readl(pmc + PMC_SCRATCH0);
+	pmc_32kwritel(reg | 1, PMC_SCRATCH0);
+
+	pmc_32kwritel(tegra_lp0_vec_start, PMC_SCRATCH1);
+}
+
+static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = {
+	[TEGRA_SUSPEND_NONE] = "none",
+	[TEGRA_SUSPEND_LP2] = "LP2",
+	[TEGRA_SUSPEND_LP1] = "LP1",
+	[TEGRA_SUSPEND_LP0] = "LP0",
+};
+
+static int tegra_suspend_enter(suspend_state_t state)
+{
+	enum tegra_suspend_mode mode = current_suspend_mode;
+
+	BUG_ON(mode < 0 || mode >= TEGRA_MAX_SUSPEND_MODE);
+
+	if ((mode == TEGRA_SUSPEND_LP0) && !tegra_pm_irq_lp0_allowed()) {
+		pr_info("LP0 not used due to unsupported wakeup events\n");
+		mode = TEGRA_SUSPEND_LP1;
+	}
+
+	tegra_common_suspend();
+
+	pr_info("Entering suspend state %s\n", lp_state[mode]);
+
+	tegra_pm_set(mode);
+
+	local_fiq_disable();
+
+	cpu_pm_enter();
+	cpu_complex_pm_enter();
+
+	suspend_cpu_complex();
+	flush_cache_all();
+	outer_flush_all();
+	outer_disable();
+
+	if (mode == TEGRA_SUSPEND_LP2)
+		tegra_sleep_cpu(PLAT_PHYS_OFFSET - PAGE_OFFSET);
+	else
+		tegra_sleep_core(PLAT_PHYS_OFFSET - PAGE_OFFSET);
+
+	tegra_init_cache();
+	restore_cpu_complex();
+
+	cpu_complex_pm_exit();
+	cpu_pm_exit();
+
+	local_fiq_enable();
+
+	tegra_common_resume();
+
+	return 0;
+}
+
+static const struct platform_suspend_ops tegra_suspend_ops = {
+	.valid		= suspend_valid_only_mem,
+	.prepare_late	= tegra_suspend_prepare_late,
+	.wake		= tegra_suspend_wake,
+	.enter		= tegra_suspend_enter,
+};
+#endif
+
+void __init tegra_init_suspend(struct tegra_suspend_platform_data *plat)
+{
+	u32 reg;
+	u32 mode;
+
+	tegra_pclk = clk_get_sys(NULL, "pclk");
+	BUG_ON(IS_ERR(tegra_pclk));
+	pdata = plat;
+	(void)reg;
+	(void)mode;
+
+	create_suspend_pgtable();
+
+#ifdef CONFIG_PM
+	if (plat->suspend_mode == TEGRA_SUSPEND_LP0 && !tegra_lp0_vec_size) {
+		pr_warning("Suspend mode LP0 requested, no lp0_vec\n");
+		pr_warning("Disabling LP0\n");
+		plat->suspend_mode = TEGRA_SUSPEND_LP1;
+	}
+
+	iram_save_size = &tegra_iram_end - &tegra_iram_start;
+
+	iram_save = kmalloc(iram_save_size, GFP_KERNEL);
+	if (!iram_save) {
+		pr_err("%s: unable to allocate memory for SDRAM self-refresh "
+		       "LP0/LP1 unavailable\n", __func__);
+		plat->suspend_mode = TEGRA_SUSPEND_LP2;
+	}
+
+	/* Initialize scratch registers used for CPU LP2 synchronization */
+	writel(0, pmc + PMC_SCRATCH37);
+	writel(0, pmc + PMC_SCRATCH38);
+	writel(0, pmc + PMC_SCRATCH39);
+	writel(0, pmc + PMC_SCRATCH41);
+
+	/* Always enable CPU power request; just normal polarity is supported */
+	reg = readl(pmc + PMC_CTRL);
+	BUG_ON(reg & TEGRA_POWER_CPU_PWRREQ_POLARITY);
+	reg |= TEGRA_POWER_CPU_PWRREQ_OE;
+	pmc_32kwritel(reg, PMC_CTRL);
+
+	/* Configure core power request and system clock control if LP0
+	   is supported */
+	writel(pdata->core_timer, pmc + PMC_COREPWRGOOD_TIMER);
+	writel(pdata->core_off_timer, pmc + PMC_COREPWROFF_TIMER);
+
+	reg = readl(pmc + PMC_CTRL);
+
+	if (!pdata->sysclkreq_high)
+		reg |= TEGRA_POWER_SYSCLK_POLARITY;
+	else
+		reg &= ~TEGRA_POWER_SYSCLK_POLARITY;
+
+	if (!pdata->corereq_high)
+		reg |= TEGRA_POWER_PWRREQ_POLARITY;
+	else
+		reg &= ~TEGRA_POWER_PWRREQ_POLARITY;
+
+	/* configure output inverters while the request is tristated */
+	pmc_32kwritel(reg, PMC_CTRL);
+
+	/* now enable requests */
+	reg |= TEGRA_POWER_SYSCLK_OE;
+	reg |= TEGRA_POWER_PWRREQ_OE;
+	pmc_32kwritel(reg, PMC_CTRL);
+
+	if (pdata->suspend_mode == TEGRA_SUSPEND_LP0)
+		tegra2_lp0_suspend_init();
+
+	suspend_set_ops(&tegra_suspend_ops);
+#endif
+
+	current_suspend_mode = plat->suspend_mode;
+}
+
+static int tegra_debug_uart_suspend(void)
+{
+	void __iomem *uart;
+	u32 lcr;
+
+	if (TEGRA_DEBUG_UART_BASE == 0)
+		return 0;
+
+	uart = IO_ADDRESS(TEGRA_DEBUG_UART_BASE);
+
+	lcr = readb(uart + UART_LCR * 4);
+
+	tegra_sctx.uart[0] = lcr;
+	tegra_sctx.uart[1] = readb(uart + UART_MCR * 4);
+
+	/* DLAB = 0 */
+	writeb(lcr & ~UART_LCR_DLAB, uart + UART_LCR * 4);
+
+	tegra_sctx.uart[2] = readb(uart + UART_IER * 4);
+
+	/* DLAB = 1 */
+	writeb(lcr | UART_LCR_DLAB, uart + UART_LCR * 4);
+
+	tegra_sctx.uart[3] = readb(uart + UART_DLL * 4);
+	tegra_sctx.uart[4] = readb(uart + UART_DLM * 4);
+
+	writeb(lcr, uart + UART_LCR * 4);
+
+	return 0;
+}
+
+static void tegra_debug_uart_resume(void)
+{
+	void __iomem *uart;
+	u32 lcr;
+
+	if (TEGRA_DEBUG_UART_BASE == 0)
+		return;
+
+	uart = IO_ADDRESS(TEGRA_DEBUG_UART_BASE);
+
+	lcr = tegra_sctx.uart[0];
+
+	writeb(tegra_sctx.uart[1], uart + UART_MCR * 4);
+
+	/* DLAB = 0 */
+	writeb(lcr & ~UART_LCR_DLAB, uart + UART_LCR * 4);
+
+	writeb(tegra_sctx.uart[2], uart + UART_IER * 4);
+
+	/* DLAB = 1 */
+	writeb(lcr | UART_LCR_DLAB, uart + UART_LCR * 4);
+
+	writeb(tegra_sctx.uart[3], uart + UART_DLL * 4);
+	writeb(tegra_sctx.uart[4], uart + UART_DLM * 4);
+
+	writeb(lcr, uart + UART_LCR * 4);
+}
+
+static struct syscore_ops tegra_debug_uart_syscore_ops = {
+	.suspend = tegra_debug_uart_suspend,
+	.resume = tegra_debug_uart_resume,
+};
+
+static int tegra_debug_uart_syscore_init(void)
+{
+	register_syscore_ops(&tegra_debug_uart_syscore_ops);
+	return 0;
+}
+arch_initcall(tegra_debug_uart_syscore_init);
+
+#ifdef CONFIG_DEBUG_FS
+static const char *tegra_suspend_name[TEGRA_MAX_SUSPEND_MODE] = {
+	[TEGRA_SUSPEND_NONE]	= "none",
+	[TEGRA_SUSPEND_LP2]	= "lp2",
+	[TEGRA_SUSPEND_LP1]	= "lp1",
+	[TEGRA_SUSPEND_LP0]	= "lp0",
+};
+
+static int tegra_suspend_debug_show(struct seq_file *s, void *data)
+{
+	seq_printf(s, "%s\n", tegra_suspend_name[*(int *)s->private]);
+	return 0;
+}
+
+static int tegra_suspend_debug_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, tegra_suspend_debug_show, inode->i_private);
+}
+
+static int tegra_suspend_debug_write(struct file *file,
+	const char __user *user_buf, size_t count, loff_t *ppos)
+{
+	char buf[32];
+	int buf_size;
+	int i;
+	struct seq_file *s = file->private_data;
+	enum tegra_suspend_mode *val = s->private;
+
+	memset(buf, 0x00, sizeof(buf));
+	buf_size = min(count, (sizeof(buf)-1));
+	if (copy_from_user(buf, user_buf, buf_size))
+		return -EFAULT;
+
+	for (i = 0; i < TEGRA_MAX_SUSPEND_MODE; i++) {
+		if (!strnicmp(buf, tegra_suspend_name[i],
+		    strlen(tegra_suspend_name[i]))) {
+			if (i > pdata->suspend_mode)
+				return -EINVAL;
+			*val = i;
+			return count;
+		}
+	}
+
+	return -EINVAL;
+}
+
+static const struct file_operations tegra_suspend_debug_fops = {
+	.open		= tegra_suspend_debug_open,
+	.write		= tegra_suspend_debug_write,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
+static int __init tegra_suspend_debug_init(void)
+{
+	struct dentry *d;
+
+	d = debugfs_create_file("suspend_mode", 0755, NULL,
+		(void *)&current_suspend_mode, &tegra_suspend_debug_fops);
+	if (!d) {
+		pr_info("Failed to create suspend_mode debug file\n");
+		return -ENOMEM;
+	}
+
+	return 0;
+}
+
+late_initcall(tegra_suspend_debug_init);
+#endif
diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h
new file mode 100644
index 000000000000..e855b9d19301
--- /dev/null
+++ b/arch/arm/mach-tegra/pm.h
@@ -0,0 +1,52 @@
+/*
+ * arch/arm/mach-tegra/include/mach/suspend.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Colin Cross <ccross@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+
+#ifndef _MACH_TEGRA_SUSPEND_H_
+#define _MACH_TEGRA_SUSPEND_H_
+
+enum tegra_suspend_mode {
+	TEGRA_SUSPEND_NONE = 0,
+	TEGRA_SUSPEND_LP2,	/* CPU voltage off */
+	TEGRA_SUSPEND_LP1,	/* CPU voltage off, DRAM self-refresh */
+	TEGRA_SUSPEND_LP0,	/* CPU + core voltage off, DRAM self-refresh */
+	TEGRA_MAX_SUSPEND_MODE,
+};
+
+struct tegra_suspend_platform_data {
+	unsigned long cpu_timer;   /* CPU power good time in us,  LP2/LP1 */
+	unsigned long cpu_off_timer;	/* CPU power off time us, LP2/LP1 */
+	unsigned long core_timer;  /* core power good time in ticks,  LP0 */
+	unsigned long core_off_timer;	/* core power off time ticks, LP0 */
+	bool corereq_high;         /* Core power request active-high */
+	bool sysclkreq_high;       /* System clock request is active-high */
+	enum tegra_suspend_mode suspend_mode;
+};
+
+unsigned long tegra_cpu_power_good_time(void);
+unsigned long tegra_cpu_power_off_time(void);
+
+void tegra2_lp0_suspend_init(void);
+void __init tegra_init_suspend(struct tegra_suspend_platform_data *plat);
+
+void tegra_idle_lp2(void);
+
+u64 tegra_rtc_read_ms(void);
+
+#endif /* _MACH_TEGRA_SUSPEND_H_ */
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
new file mode 100644
index 000000000000..0c74e4ecd774
--- /dev/null
+++ b/arch/arm/mach-tegra/sleep.S
@@ -0,0 +1,745 @@
+/*
+ * Copyright (c) 2010, NVIDIA Corporation.
+ * Copyright (c) 2011, Google, Inc.
+ *
+ * Author: Colin Cross <ccross@android.com>
+ *         Gary King <gking@nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/const.h>
+#include <linux/init.h>
+#include <linux/linkage.h>
+
+#include <asm/assembler.h>
+#include <asm/cache.h>
+#include <asm/domain.h>
+#include <asm/memory.h>
+#include <asm/page.h>
+#include <asm/ptrace.h>
+#include <asm/asm-offsets.h>
+#include <asm/glue-cache.h>
+#include <asm/glue-proc.h>
+#include <asm/system.h>
+
+#include <mach/iomap.h>
+#include <mach/io.h>
+
+#include "sleep.h"
+
+#define EMC_CFG				0xc
+#define EMC_ADR_CFG			0x10
+#define EMC_REFRESH			0x70
+#define EMC_NOP				0xdc
+#define EMC_SELF_REF			0xe0
+#define EMC_REQ_CTRL			0x2b0
+#define EMC_EMC_STATUS			0x2b4
+
+#define CLK_RESET_CCLK_BURST		0x20
+#define CLK_RESET_CCLK_DIVIDER		0x24
+#define CLK_RESET_SCLK_BURST		0x28
+#define CLK_RESET_SCLK_DIVIDER		0x2c
+
+#define CLK_RESET_PLLC_BASE		0x80
+#define CLK_RESET_PLLM_BASE		0x90
+#define CLK_RESET_PLLP_BASE		0xa0
+#define CLK_RESET_PLLP_OUTA		0xa4
+#define CLK_RESET_PLLP_OUTB		0xa8
+#define CLK_RESET_PLLP_MISC		0xac
+#define CLK_RESET_PLLX_BASE		0xe0
+#define CLK_RESET_PLLX_MISC		0xe4
+
+#define FLOW_CTRL_WAITEVENT		(2 << 29)
+#define FLOW_CTRL_STOP_UNTIL_IRQ	(4 << 29)
+#define FLOW_CTRL_JTAG_RESUME		(1 << 28)
+#define FLOW_CTRL_IRQ_RESUME		(1 << 10)
+#define FLOW_CTRL_FIQ_RESUME		(1 << 8)
+
+#define TEGRA_PMC_VIRT		(TEGRA_PMC_BASE - IO_APB_PHYS + IO_APB_VIRT)
+#define TEGRA_ARM_PERIF_VIRT	(TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS + IO_CPU_VIRT)
+#define TEGRA_FLOW_CTRL_VIRT	(TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS + IO_PPSB_VIRT)
+#define TEGRA_CLK_RESET_VIRT	(TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS + IO_PPSB_VIRT)
+
+/* returns the offset of the flow controller halt register for a cpu */
+.macro cpu_to_halt_reg rd, rcpu
+	cmp	\rcpu, #0
+	subne	\rd, \rcpu, #1
+	movne	\rd, \rd, lsl #3
+	addne	\rd, \rd, #0x14
+	moveq	\rd, #0
+.endm
+
+/* returns the ID of the current processor */
+.macro cpu_id, rd
+	mrc	p15, 0, \rd, c0, c0, 5
+	and	\rd, \rd, #0xF
+.endm
+
+/*
+ * tegra_pen_lock
+ *
+ * spinlock implementation with no atomic test-and-set and no coherence
+ * using Peterson's algorithm on strongly-ordered registers
+ * used to synchronize a cpu waking up from wfi with entering lp2 on idle
+ *
+ * SCRATCH37 = r1 = !turn (inverted from Peterson's algorithm)
+ * on cpu 0:
+ * SCRATCH38 = r2 = flag[0]
+ * SCRATCH39 = r3 = flag[1]
+ * on cpu1:
+ * SCRATCH39 = r2 = flag[1]
+ * SCRATCH38 = r3 = flag[0]
+ *
+ * must be called with MMU on
+ * corrupts r0-r3, r12
+ */
+ENTRY(tegra_pen_lock)
+	ldr	r3, =TEGRA_PMC_VIRT
+	cpu_id	r0
+	add	r1, r3, #PMC_SCRATCH37
+	cmp	r0, #0
+	addeq	r2, r3, #PMC_SCRATCH38
+	addeq	r3, r3, #PMC_SCRATCH39
+	addne	r2, r3, #PMC_SCRATCH39
+	addne	r3, r3, #PMC_SCRATCH38
+
+	mov	r12, #1
+	str	r12, [r2]		@ flag[cpu] = 1
+	dsb
+	str	r12, [r1]		@ !turn = cpu
+1:	dsb
+	ldr	r12, [r3]
+	cmp	r12, #1			@ flag[!cpu] == 1?
+	ldreq	r12, [r1]
+	cmpeq	r12, r0			@ !turn == cpu?
+	beq	1b			@ while !turn == cpu && flag[!cpu] == 1
+
+	mov	pc, lr			@ locked
+ENDPROC(tegra_pen_lock)
+
+ENTRY(tegra_pen_unlock)
+	dsb
+	ldr	r3, =TEGRA_PMC_VIRT
+	cpu_id	r0
+	cmp	r0, #0
+	addeq	r2, r3, #PMC_SCRATCH38
+	addne	r2, r3, #PMC_SCRATCH39
+	mov	r12, #0
+	str	r12, [r2]
+	mov	pc, lr
+ENDPROC(tegra_pen_unlock)
+
+ENTRY(tegra_cpu_set_resettable_soon)
+	ldr	r3, =TEGRA_PMC_VIRT
+	add	r1, r3, #PMC_SCRATCH41
+	mov	r12, #CPU_RESETTABLE_SOON
+	str	r12, [r1]
+	mov	pc, lr
+ENDPROC(tegra_cpu_set_resettable_soon)
+
+ENTRY(tegra_cpu_is_resettable_soon)
+	ldr	r3, =TEGRA_PMC_VIRT
+	add	r1, r3, #PMC_SCRATCH41
+	ldr	r12, [r1]
+	cmp	r12, #CPU_RESETTABLE_SOON
+	moveq	r0, #1
+	movne	r0, #0
+	mov	pc, lr
+ENDPROC(tegra_cpu_is_resettable_soon)
+
+/*
+ * tegra_cpu_save
+ *
+ * r0 = v2p
+ * r3 = resume address
+ * saves r4-r11 on the stack
+ * modifies sp, returns the sp after saving registers but before cpu_suspend,
+ *   appropriate for restoring an aborted suspend that does not call cpu_resume
+ * corrupts r1, r3-r6, r9, r10
+ */
+
+ENTRY(tegra_cpu_save)
+	stmfd	sp!, {r4 - r11}
+	stmfd	sp!, {r3}
+	mrc	p15, 0, r4, c15, c0, 1	@ read diagnostic register
+	stmfd	sp!, {r4}
+
+	adr	r3, tegra_cpu_resume
+
+	mov	r7, sp
+	mov	r4, lr
+	mov	r5, r0
+	mov	r6, r2
+	mov	r1, r0
+	bl	cpu_suspend
+	mov	lr, r4
+	mov	r0, r5
+	mov	r2, r6
+	mov	sp, r7
+
+	mov	r4, #0
+	mcr	p15, 0, r4, c1, c0, 1	@ exit coherency
+	isb
+	cpu_id	r4
+	ldr	r5, =TEGRA_ARM_PERIF_VIRT + 0xC
+	mov	r4, r4, lsl #2
+	mov	r6, #0xf
+	mov	r6, r6, lsl r4
+	str	r6, [r5]		@ invalidate SCU tags for CPU
+
+	mov	pc, lr
+ENDPROC(tegra_cpu_save)
+
+/*
+ * tegra_cpu_wfi
+ *
+ * puts current CPU in clock-gated wfi using the flow controller
+ * if the state is saved before calling tegra_cpu_wfi, the cpu can go from
+ * wfi directly to reset
+ *
+ * corrupts r0-r2
+ * must be called with MMU on
+ */
+ENTRY(tegra_cpu_wfi)
+	cpu_id	r0
+	cpu_to_halt_reg r1, r0
+	ldr	r0, =TEGRA_FLOW_CTRL_VIRT
+	mov	r2, #FLOW_CTRL_WAITEVENT | FLOW_CTRL_JTAG_RESUME
+	str	r2, [r0, r1]		@ put flow controller in wait event mode
+	ldr	r2, [r0, r1]
+	isb
+	dsb
+	wfi
+	mov	r2, #0
+	str	r2, [r0, r1]
+	ldr	r2, [r0, r1]
+	mov	pc, lr
+ENDPROC(tegra_cpu_wfi)
+
+/*
+ * tegra_sleep_reset(unsigned long v2p)
+ *
+ * puts the current cpu in reset
+ * uses tegra_cpu_save to take the cpu out of coherence
+ * should never return
+ */
+ENTRY(tegra_sleep_reset)
+	bl	tegra_cpu_save
+	cpu_id	r0
+	bl	tegra_cpu_reset
+	mov	pc, lr
+ENDPROC(tegra_sleep_reset)
+
+/*
+ * tegra_sleep_core(unsigned long v2p)
+ *
+ * enters suspend in LP0 or LP1 by turning off the mmu and jumping to
+ * tegra_tear_down_core in IRAM
+ */
+ENTRY(tegra_sleep_core)
+	mov	r3, lr			@ set resume address to lr
+	bl	tegra_cpu_save
+
+	ldr	r1, =tegra_tear_down_core
+	ldr	r2, =tegra_iram_start
+	sub	r1, r1, r2
+	ldr	r2, =TEGRA_IRAM_CODE_AREA
+	add	r1, r1, r2
+	b	tegra_turn_off_mmu
+ENDPROC(tegra_sleep_core)
+
+.word
+
+/*
+ * tegra_sleep_cpu(unsigned long v2p)
+ *
+ * enters suspend in LP2 by turning off the mmu and jumping to
+ * tegra_tear_down_cpu
+ */
+ENTRY(tegra_sleep_cpu)
+	mov	r3, lr			@ set resume address to lr
+	bl	tegra_cpu_save
+
+	ldr	r1, =tegra_tear_down_cpu
+	add	r1, r1, r0
+	b	tegra_turn_off_mmu
+ENDPROC(tegra_sleep_cpu)
+
+/*
+ * tegra_sleep_wfi(unsigned long v2p)
+ */
+ENTRY(tegra_sleep_wfi)
+	mov	r3, lr			@ set resume address to lr
+	mrc	p15, 0, r2, c1, c0, 1	@ save actlr before exiting coherency
+	bl	tegra_cpu_save
+
+	mov	r11, r2
+
+	ldr	r3, =TEGRA_PMC_VIRT
+	add	r0, r3, #PMC_SCRATCH41
+	mov	r3, #CPU_RESETTABLE
+	str	r3, [r0]
+
+	bl	tegra_cpu_wfi
+
+	/*
+	 * cpu may be reset while in wfi, which will return through
+	 * tegra_secondary_resume to cpu_resume to tegra_cpu_resume
+	 * or interrupt may wake wfi, which will return here
+	 * cpu state is unchanged - MMU is on, cache is on, coherency is off
+	 *
+	 * r11 contains the original actlr
+	 */
+
+	bl	tegra_pen_lock
+
+	ldr	r3, =TEGRA_PMC_VIRT
+	add	r0, r3, #PMC_SCRATCH41
+	mov	r3, #CPU_NOT_RESETTABLE
+	str	r3, [r0]
+
+	bl	tegra_pen_unlock
+
+	mcr	p15, 0, r11, c1, c0, 1	@ reenable coherency
+
+	@ the cpu was running with coherency disabled, caches may be out of date
+#ifdef MULTI_CACHE
+	ldr	r10, =cpu_cache
+	mov	lr, pc
+	ldr	pc, [r10, #CACHE_FLUSH_KERN_ALL]
+#else
+	bl	__cpuc_flush_kern_all
+#endif
+
+	b	tegra_cpu_sleep_abort
+ENDPROC(tegra_sleep_wfi)
+
+/*
+ * tegra_cpu_resume
+ *
+ * reloads the volatile CPU state from the context area
+ * the mmu should be on and the CPU should be coherent before this is called
+ */
+	.align L1_CACHE_SHIFT
+tegra_cpu_resume:
+	mov	r0, #0
+	mcr	p15, 0, r0, c8, c3, 0	@ invalidate TLB
+	mcr	p15, 0, r0, c7, c5, 6	@ flush BTAC
+	mcr	p15, 0, r0, c7, c5, 0	@ flush instruction cache
+	dsb
+	isb
+
+	bl cpu_init
+
+tegra_cpu_sleep_abort:
+	ldmfd	sp!, {r4}
+	mcr	p15, 0, r4, c15, c0, 1	@ write diagnostic register
+	ldmfd	sp!, {lr}
+	ldmfd	sp!, {r4 - r11}
+	mov	pc, lr
+
+/*
+ * tegra_cpu_reset
+ *
+ * r0 is cpu to reset
+ *
+ * puts the specified CPU in wait-for-event mode on the flow controller
+ * and puts the CPU in reset
+ * can be called on the current cpu or another cpu
+ * if called on the current cpu, does not return
+ *
+ * corrupts r0-r3, r12
+ */
+ENTRY(tegra_cpu_reset)
+	ldr	r3, =TEGRA_PMC_VIRT
+	add	r1, r3, #PMC_SCRATCH41
+	mov	r12, #CPU_RESETTABLE
+	str	r12, [r1]
+
+	cpu_to_halt_reg r1, r0
+	ldr	r3, =TEGRA_FLOW_CTRL_VIRT
+	mov	r2, #FLOW_CTRL_WAITEVENT | FLOW_CTRL_JTAG_RESUME
+	str	r2, [r3, r1]		@ put flow controller in wait event mode
+	ldr	r2, [r3, r1]
+	isb
+	dsb
+	movw	r1, 0x1011
+	mov	r1, r1, lsl r0
+	ldr	r3, =TEGRA_CLK_RESET_VIRT
+	str	r1, [r3, #0x340]	@ put slave CPU in reset
+	isb
+	dsb
+	cpu_id	r3
+	cmp	r3, r0
+	beq	.
+	mov	pc, lr
+ENDPROC(tegra_cpu_reset)
+
+/*
+ * tegra_turn_off_mmu
+ *
+ * r0 = v2p
+ * r1 = physical address to jump to with mmu off
+ */
+tegra_turn_off_mmu:
+	/*
+	 * change page table pointer to tegra_pgd_phys, so that IRAM
+	 * and MMU shut-off will be mapped virtual == physical
+	 */
+	mrc	p15, 0, r2, c2, c0, 0	@ TTB 0
+	ldr	r3, =~PAGE_MASK
+	and	r2, r2, r3
+	ldr	r3, tegra_pgd_phys_address
+	ldr	r3, [r3]
+	orr	r3, r3, r2
+	mov	r2, #0
+	mcr	p15, 0, r2, c13, c0, 1	@ reserved context
+	isb
+	mcr	p15, 0, r3, c2, c0, 0	@ TTB 0
+	isb
+
+	mov	r2, #0
+	mcr	p15, 0, r2, c8, c3, 0	@ invalidate TLB
+	mcr	p15, 0, r2, c7, c5, 6	@ flush BTAC
+	mcr	p15, 0, r2, c7, c5, 0	@ flush instruction cache
+
+	ldr	r3, =tegra_shut_off_mmu
+	add	r3, r3, r0
+	mov	r0, r1
+	mov	pc, r3
+
+tegra_pgd_phys_address:
+	.word	tegra_pgd_phys
+
+/*
+ * tegra_shut_off_mmu
+ *
+ * r0 = physical address to jump to with mmu off
+ *
+ * called with VA=PA mapping
+ * turns off MMU, icache, dcache and branch prediction
+ */
+tegra_shut_off_mmu:
+	mrc	p15, 0, r3, c1, c0, 0
+	movw	r2, #(1 << 12) | (1 << 11) | (1 << 2) | (1 << 0)
+	bic	r3, r3, r2
+	dsb
+	mcr	p15, 0, r3, c1, c0, 0
+	isb
+	mov	pc, r0
+
+	.ltorg
+
+/*
+ * tegra_cpu_clk32k
+ *
+ * In LP2 the normal cpu clock pllx will be turned off. Switch the CPU to pllp
+ */
+ tegra_cpu_pllp:
+	/* in LP2 idle (SDRAM active), set the CPU burst policy to PLLP */
+	ldr	r5, =TEGRA_CLK_RESET_BASE
+	mov	r0, #(2 << 28)	/* burst policy = run mode */
+	orr	r0, r0, #(4 << 4) /* use PLLP in run mode burst */
+	str	r0, [r5, #CLK_RESET_CCLK_BURST]
+	mov	r0, #0
+	str	r0, [r5, #CLK_RESET_CCLK_DIVIDER]
+	mov	pc, lr
+
+tegra_tear_down_cpu:
+	bl	tegra_cpu_pllp
+	b	tegra_enter_sleep
+
+/* START OF ROUTINES COPIED TO IRAM */
+	.align L1_CACHE_SHIFT
+	.globl tegra_iram_start
+tegra_iram_start:
+
+/*
+ * tegra_tear_down_core
+ *
+ * copied into and executed from IRAM
+ * puts memory in self-refresh for LP0 and LP1
+ */
+tegra_tear_down_core:
+	bl	tegra_sdram_self_refresh
+	bl	tegra_cpu_clk32k
+	b	tegra_enter_sleep
+
+/*
+ * tegra_cpu_clk32k
+ *
+ * In LP0 and LP1 all plls will be turned off.  Switch the CPU and system clock
+ * to the 32khz clock (clks)
+ */
+tegra_cpu_clk32k:
+	/* start by jumping to clkm to safely disable PLLs, then jump
+	 * to clks */
+	mov	r0, #(1 << 28)
+	str	r0, [r5, #CLK_RESET_SCLK_BURST]
+	str	r0, [r5, #CLK_RESET_CCLK_BURST]
+	mov	r0, #0
+	str	r0, [r5, #CLK_RESET_CCLK_DIVIDER]
+	str	r0, [r5, #CLK_RESET_SCLK_DIVIDER]
+
+	/* 2 us delay between changing sclk and disabling PLLs */
+	ldr	r7, =TEGRA_TMRUS_BASE
+	ldr	r1, [r7]
+	add	r1, r1, #3
+
+1:	ldr	r0, [r7]
+	cmp	r0, r1
+	dmb
+	bmi	1b
+
+	/* switch to CLKS */
+	mov	r0, #0	/* burst policy = 32KHz */
+	str	r0, [r5, #CLK_RESET_SCLK_BURST]
+
+	/* disable PLLP, PLLM, PLLC in LP0 and LP1 states */
+	ldr	r0, [r5, #CLK_RESET_PLLM_BASE]
+	bic	r0, r0, #(1 << 30)
+	str	r0, [r5, #CLK_RESET_PLLM_BASE]
+	ldr	r0, [r5, #CLK_RESET_PLLP_BASE]
+	bic	r0, r0, #(1 << 30)
+	str	r0, [r5, #CLK_RESET_PLLP_BASE]
+	ldr	r0, [r5, #CLK_RESET_PLLC_BASE]
+	bic	r0, r0, #(1 << 30)
+	str	r0, [r5, #CLK_RESET_PLLC_BASE]
+	mov	pc, lr
+
+/*
+ * tegra_enter_sleep
+ *
+ * uses flow controller to enter sleep state
+ * executes from IRAM with SDRAM in selfrefresh when target state is LP0 and LP1
+ * executes from SDRAM with target state is LP2
+ */
+tegra_enter_sleep:
+	ldr	r7, =TEGRA_TMRUS_BASE
+	ldr	r1, [r7]
+	ldr	r4, =TEGRA_PMC_BASE
+	str	r1, [r4, #PMC_SCRATCH38]
+	dsb
+	ldr	r6, =TEGRA_FLOW_CTRL_BASE
+
+	mov	r0, #FLOW_CTRL_STOP_UNTIL_IRQ
+	orr	r0, r0, #FLOW_CTRL_IRQ_RESUME | FLOW_CTRL_FIQ_RESUME
+	cpu_id	r1
+	cpu_to_halt_reg r1, r1
+	str	r0, [r6, r1]
+	dsb
+	ldr	r0, [r6, r1] /* memory barrier */
+
+halted: dsb
+	wfe	/* CPU should be power gated here */
+	isb
+	b	halted
+
+/*
+ * tegra_lp1_reset
+ *
+ * reset vector for LP1 restore; copied into IRAM during suspend.
+ * brings the system back up to a safe starting point (SDRAM out of
+ * self-refresh, PLLC, PLLM and PLLP reenabled, CPU running on PLLP,
+ * system clock running on the same PLL that it suspended at), and
+ * jumps to tegra_lp2_startup to restore PLLX and virtual addressing.
+ * physical address of tegra_lp2_startup expected to be stored in
+ * PMC_SCRATCH41
+ */
+ENTRY(tegra_lp1_reset)
+	/*
+	 * the CPU and system bus are running at 32KHz and executing from
+	 * IRAM when this code is executed; immediately switch to CLKM and
+	 * enable PLLP.
+	 */
+	ldr	r0, =TEGRA_CLK_RESET_BASE
+	mov	r1, #(1 << 28)
+	str	r1, [r0, #CLK_RESET_SCLK_BURST]
+	str	r1, [r0, #CLK_RESET_CCLK_BURST]
+	mov	r1, #0
+	str	r1, [r0, #CLK_RESET_SCLK_DIVIDER]
+	str	r1, [r0, #CLK_RESET_CCLK_DIVIDER]
+
+	ldr	r1, [r0, #CLK_RESET_PLLM_BASE]
+	tst	r1, #(1 << 30)
+	orreq	r1, r1, #(1 << 30)
+	streq	r1, [r0, #CLK_RESET_PLLM_BASE]
+	ldr	r1, [r0, #CLK_RESET_PLLP_BASE]
+	tst	r1, #(1 << 30)
+	orreq	r1, r1, #(1 << 30)
+	streq	r1, [r0, #CLK_RESET_PLLP_BASE]
+	ldr	r1, [r0, #CLK_RESET_PLLC_BASE]
+	tst	r1, #(1 << 30)
+	orreq	r1, r1, #(1 << 30)
+	streq	r1, [r0, #CLK_RESET_PLLC_BASE]
+
+	adr	r2, tegra_sdram_pad_address
+	adr	r4, tegra_sdram_pad_save
+	mov	r5, #0
+
+padload:
+	ldr	r0, [r2, r5]		@ r0 is emc register address
+
+	ldr	r1, [r4, r5]
+	str	r1, [r0]		@ set emc register to safe vals
+
+	add	r5, r5, #4
+	ldr	r0, tegra_sdram_pad_size
+	cmp	r0, r5
+	bne	padload
+
+padload_done:
+	ldr	r7, =TEGRA_TMRUS_BASE
+	ldr	r1, [r7]
+	add	r1, r1, #0xff		@ 255uS delay for PLL stabilization
+
+1:	ldr	r0, [r7]
+	cmp	r0, r1
+	dmb
+	bmi	1b
+
+	adr	r4, tegra_sclk_save
+	ldr	r4, [r4]
+	ldr	r0, =TEGRA_CLK_RESET_BASE
+	str	r4, [r0, #CLK_RESET_SCLK_BURST]
+	ldr	r4, =((1 << 28) | (4))	@ burst policy is PLLP
+	str	r4, [r0, #CLK_RESET_CCLK_BURST]
+
+	ldr	r0, =TEGRA_EMC_BASE
+	ldr	r1, [r0, #EMC_CFG]
+	bic	r1, r1, #(1 << 31)	@ disable DRAM_CLK_STOP
+	str	r1, [r0, #EMC_CFG]
+
+	mov	r1, #0
+	str	r1, [r0, #EMC_SELF_REF]	@ take DRAM out of self refresh
+	mov	r1, #1
+	str	r1, [r0, #EMC_NOP]
+	str	r1, [r0, #EMC_NOP]
+	str	r1, [r0, #EMC_REFRESH]
+
+	ldr	r1, [r0, #EMC_ADR_CFG]
+	tst	r1, #(0x3 << 24)
+	moveq	r1, #(0x1 << 8)		@ just 1 device
+	movne	r1, #(0x3 << 8)		@ 2 devices
+
+exit_selfrefresh_loop:
+	ldr	r2, [r0, #EMC_EMC_STATUS]
+	ands	r2, r2, r1
+	bne	exit_selfrefresh_loop
+
+	mov	r1, #0
+	str	r1, [r0, #EMC_REQ_CTRL]
+
+	ldr	r0, =TEGRA_PMC_BASE
+	ldr	r0, [r0, #PMC_SCRATCH41]
+	mov	pc, r0
+ENDPROC(tegra_lp1_reset)
+
+/*
+ * tegra_sdram_self_refresh
+ *
+ * called with MMU off and caches disabled
+ * puts sdram in self refresh
+ * must execute from IRAM
+ */
+tegra_sdram_self_refresh:
+	ldr	r1, =TEGRA_EMC_BASE
+	mov	r2, #3
+	str	r2, [r1, #EMC_REQ_CTRL]		@ stall incoming DRAM requests
+
+emcidle:ldr	r2, [r1, #EMC_EMC_STATUS]
+	tst	r2, #4
+	beq	emcidle
+
+	mov	r2, #1
+	str	r2, [r1, #EMC_SELF_REF]
+
+	ldr	r2, [r1, #EMC_ADR_CFG]
+	tst	r2, #(0x3 << 24)
+	moveq	r2, #(0x1 << 8)			@ just 1 device
+	movne	r2, #(0x3 << 8)			@ 2 devices
+
+emcself:ldr	r3, [r1, #EMC_EMC_STATUS]
+	and	r3, r3, r2
+	cmp	r3, r2
+	bne	emcself				@ loop until DDR in self-refresh
+
+	adr	r2, tegra_sdram_pad_address
+	adr	r3, tegra_sdram_pad_safe
+	adr	r4, tegra_sdram_pad_save
+	mov	r5, #0
+
+padsave:
+	ldr	r0, [r2, r5]			@ r0 is emc register address
+
+	ldr	r1, [r0]
+	str	r1, [r4, r5]			@ save emc register
+
+	ldr	r1, [r3, r5]
+	str	r1, [r0]			@ set emc register to safe vals
+
+	add	r5, r5, #4
+	ldr	r0, tegra_sdram_pad_size
+	cmp	r0, r5
+	bne	padsave
+padsave_done:
+
+	ldr	r5, =TEGRA_CLK_RESET_BASE
+	ldr	r0, [r5, #CLK_RESET_SCLK_BURST]
+	adr	r2, tegra_sclk_save
+	str	r0, [r2]
+	dsb
+	mov	pc, lr
+
+tegra_sdram_pad_address:
+	.word	TEGRA_APB_MISC_BASE + 0x8c8 /* XM2CFGCPADCTRL */
+	.word	TEGRA_APB_MISC_BASE + 0x8cc /* XM2CFGDPADCTRL */
+	.word	TEGRA_APB_MISC_BASE + 0x8d0 /* XM2CLKCFGPADCTRL */
+	.word	TEGRA_APB_MISC_BASE + 0x8d4 /* XM2COMPPADCTRL */
+	.word	TEGRA_APB_MISC_BASE + 0x8d8 /* XM2VTTGENPADCTRL */
+	.word	TEGRA_APB_MISC_BASE + 0x8e4 /* XM2CFGCPADCTRL2 */
+	.word	TEGRA_APB_MISC_BASE + 0x8e8 /* XM2CFGDPADCTRL2 */
+
+tegra_sdram_pad_size:
+	.word	tegra_sdram_pad_size - tegra_sdram_pad_address
+
+tegra_sdram_pad_safe:
+	.word	0x8
+	.word	0x8
+	.word	0x0
+	.word	0x8
+	.word	0x5500
+	.word	0x08080040
+	.word	0x0
+
+tegra_sclk_save:
+	.word	0x0
+
+tegra_sdram_pad_save:
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+	.word	0
+
+	.ltorg
+/* dummy symbol for end of IRAM */
+	.align L1_CACHE_SHIFT
+	.globl tegra_iram_end
+tegra_iram_end:
+	b	.
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
new file mode 100644
index 000000000000..0c007139b483
--- /dev/null
+++ b/arch/arm/mach-tegra/sleep.h
@@ -0,0 +1,64 @@
+/*
+ * arch/arm/mach-tegra/power.h
+ *
+ * Declarations for power state transition code
+ *
+ * Copyright (c) 2010, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __MACH_TEGRA_POWER_H
+#define __MACH_TEGRA_POWER_H
+
+#include <mach/iomap.h>
+
+#define TEGRA_IRAM_CODE_AREA		(TEGRA_IRAM_BASE + SZ_4K)
+
+/* PMC_SCRATCH37-39 and 41 are used for tegra_pen_lock in idle */
+#define PMC_SCRATCH37                   0x130
+#define PMC_SCRATCH38                   0x134
+/* PMC_SCRATCH39 stores the reset vector of the AVP (always 0) after LP0 */
+#define PMC_SCRATCH39                   0x138
+/* PMC_SCRATCH41 stores the reset vector of the CPU after LP0 and LP1 */
+#define PMC_SCRATCH41                   0x140
+
+#define CPU_RESETTABLE			2
+#define CPU_RESETTABLE_SOON		1
+#define CPU_NOT_RESETTABLE		0
+
+#ifndef __ASSEMBLY__
+/* assembly routines implemented in sleep.S */
+void tegra_pen_lock(void);
+void tegra_pen_unlock(void);
+void tegra_cpu_wfi(void);
+void tegra_cpu_reset(int cpu);
+void tegra_cpu_set_resettable_soon(void);
+int tegra_cpu_is_resettable_soon(void);
+
+extern void tegra_lp1_reset;
+extern void tegra_iram_start;
+extern void tegra_iram_end;
+
+void tegra_sleep_reset(void);
+void tegra_sleep_wfi(unsigned long v2p);
+void tegra_sleep_cpu(unsigned long v2p);
+void tegra_sleep_core(unsigned long v2p);
+void tegra_resume(void);
+void tegra_secondary_resume(void);
+
+#endif
+
+#endif