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authorBo Yan <byan@nvidia.com>2012-12-15 14:53:50 -0800
committerRiham Haidar <rhaidar@nvidia.com>2013-02-13 12:28:39 -0800
commit91386b6173bcc256b38e6e3bb6f29b1edccfbf90 (patch)
tree430d1604f9c2ffbb07bad6a0b3cc0cb7e45c0b90
parent79faef4783ff207f38d76c283704e3b70ea31f18 (diff)
ARM: tegra: Get cluster ID by reading MPIDR
This is to avoid MMIO access, thus save a few processor cycles. Change-Id: Ib4a2aaf8e991885baab51cd74a37387e91cfb5a8 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: http://git-master/r/171656 (cherry picked from commit 10b7f4ccbf961cbde6b2dec5eb789c1d3beb0f75) Reviewed-on: http://git-master/r/198890 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> GVS: Gerrit_Virtual_Submit
-rw-r--r--arch/arm/mach-tegra/headsmp.S4
-rw-r--r--arch/arm/mach-tegra/pm.h11
2 files changed, 8 insertions, 7 deletions
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
index 0d5b9364cdaa..75e61490978e 100644
--- a/arch/arm/mach-tegra/headsmp.S
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -200,8 +200,8 @@ __invalidate_cpu_state:
mcreq p15, 0x1, r0, c15, c0, 3
/* This is only needed for cluster 0 with integrated L2 cache */
- mov32 r0, TEGRA_FLOW_CTRL_BASE+0x2c @ CLUSTER_CONTROL
- ldr r0, [r0]
+ mrc p15, 0, r0, c0, c0, 5
+ ubfx r0, r0, #8, #4
tst r0, #1
bne __enable_i_cache_branch_pred
mrc p15, 0x1, r0, c9, c0, 2
diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h
index aad9c49d5da9..337293a2645e 100644
--- a/arch/arm/mach-tegra/pm.h
+++ b/arch/arm/mach-tegra/pm.h
@@ -97,9 +97,6 @@ bool tegra_set_cpu_in_pd(int cpu);
int tegra_suspend_dram(enum tegra_suspend_mode mode, unsigned int flags);
-#define FLOW_CTRL_CLUSTER_CONTROL \
- (IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + 0x2c)
-
#define FLOW_CTRL_CPU_PWR_CSR \
(IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + 0x38)
#define FLOW_CTRL_CPU_PWR_CSR_RAIL_ENABLE 1
@@ -152,8 +149,12 @@ static inline bool is_g_cluster_present(void)
static inline unsigned int is_lp_cluster(void)
{
unsigned int reg;
- reg = readl(FLOW_CTRL_CLUSTER_CONTROL);
- return (reg & 1); /* 0 == G, 1 == LP*/
+ asm("mrc p15, 0, %0, c0, c0, 5\n"
+ "ubfx %0, %0, #8, #4"
+ : "=r" (reg)
+ :
+ : "cc");
+ return reg ; /* 0 == G, 1 == LP*/
}
int tegra_cluster_control(unsigned int us, unsigned int flags);
void tegra_cluster_switch_prolog(unsigned int flags);